which is also the basis for [98, 99], conventional gm topologies are used in a cross-coupled manner to generate a gate bias such that it balances the core device’s current against process or temperature variations. However, these become vulnerable to supply variations and also would severely suffer from process variations when implemented in sub-nanometer technologies. In addition, like [92], these mechanisms also limit possible low voltage designs. In a distinctive approach [100], the core device is split into two halves with one half driven by a compensating gate voltage while a constant drive is applied to the other half. As a result, when there are deviations in gm, compensating voltage is generated which in turn maintains overallgm constant. Though [100] shows better results in respect of process variations, it does not yield optimum results for temperature variations. Moreover, [97,100]
does not feature any kind of feedback path for tracking LNA core device current, hence it cannot be relied upon to work in all conditions.
It is clear from these discussions that there is a need for low power, low voltage LNA that requires an effective compensation technique to tackle its performance deviations due to PVT variations. For implementation, compensation technique must let the low voltage option feasible and must utilize feedback controlling technique without actually hampering the LNA performance.
In this chapter, we present a new compensation technique that minimizes the PVT variations of the performance of the near sub-threshold operated LNA. The controlling mechanism basically involves sensing the deviation of the core device current from its nominal expected value and accordingly an error signal is generated. This error is then used to correct the drifted value by applying a variable gate bias voltage to the core device of the LNA to keep the gm constant. For implementation, the proposed technique requires an error generation circuit along with a constant current source that is used as a reference. Accordingly, a low voltage constant current reference is also realized based on a conventional PTAT current reference. However, the resulting currents are compensated with a new, simple compensating circuit technique. In addition to the benefit of minimum PVT variations with low voltage operability, the proposed scheme is a self-biased technique which does not require any additional inputs from external band-gap constant references.
4.2 Proposed compensation technique
ff fnsp tt snfp ss gm
Temp S21
Freq VDD
RB
RBIAS
M1 M2
VBIAS
Lg
Ls CC
vin
ff,1100 C ss,-200 C
Figure 4.1: The conventional biasing mechanism of LNA depicting the change in S21 due to process and temperature variations.
biasing lacks any type of controllability, the performance undergoes drastic deviations when the circuit is subjected to process, temperature and supply variations. Fig. 4.1 highlights the variation in S21, caused primarily due to the changes in gm which is because of variations in process and temperature.
Hence the LNA becomes unreliable when it is implemented with such biasing techniques. However, the same biasing concept can still be used for realizing a robust LNA if it is modified to incorporate PVT variation handling abilities. Importantly,gm of the core device has to be maintained constant. If the constantRB in Fig. 4.1 is replaced either by a variable resistance or in general a variable current source whose magnitude changes are completely mapped by LNA current variations then resulting amplifier’sgm can be stabilized.
The conceptual diagram of the proposed compensation technique is shown in Fig. 4.2. The pointers describe the feedback technique showing how the LNA current is stabilized with the help of generated intermediate voltages. It works on the principle of sensing the core device current and then correcting the current through a negative feedback mechanism. It consists of an error generator circuit that generates an error voltage by comparing a fraction of the LNA current (K.ILN A), where K is the current scaling factor, with a constant current reference (ICCR) source. Any increment or decrement in ILN A, when it is compared with ICCR, results in corresponding changes in the voltage across the node impedance, Zint that comprises of the node capacitances. This in turn acts as an error voltage
LNA
Error generator
ICCR
K.ILNA
M1 M2
M3
VBIAS
RBIAS
ILNA
VDD VDD
Bias generator
vin
ILNA K.ILNA VE
VE VBIAS ILNA Zint
Figure 4.2: The conceptual diagram of the proposed technique for PVT compensation of the LNA.
for the bias generator. The generated error voltage drives the gate of a PMOS transistor, which passes current to the diode connected NMOS, M2, and alters the current that needs to be sourced. As a result, the gate voltage to the core device is modified to the extent that brings the LNA current back to the expected value.
As ICCR is a constant current source, the change in error voltage is directly proportional to the change inILN A and is given as
∆VE α ∆ILN A (4.1)
Assuming that transistors M2 and M3 operate in weak inversion (WI) region, the current through these devices can be equated to find the effect on the resultingVBIAS i.e. isVGS2. From [101] for the current equation in WI,VBIAS can be given as
VBIAS =VGS2 =Vthn+nnvtln
"
I0p′ (WL)3
I0n′ (WL)2 exp VDD−VE−Vthp npvt
!#
(4.2)
where I0′ = I0
(WL) = µq
qǫsiN DEP
2φs vt2, with Vth, n, and vt respectively are the threshold voltage, the subthreshold swing of the device and the equivalent thermal voltage. Explanations of other parameters