6.4 Experimental Analysis
6.4.4 Effect on Tile and Chip Thermal Profile
6.4.4.1 Temporal Variation
Figure 6.12 shows the temporal change in tile temperature of Tile 7 and 10 for Body16 & Freq, respectively, while applying HB & CB independently. We fur- ther compare our policies with Greedy DVFS (GDVFS) [2], a core based DTM technique. GDVFS scales down a core’s V/F settings (at 1.5v, 1.8GHz) when its temperature goes beyond the preset value (95◦C in our work) and scales it up (at 1.65v, 2.4GHz [baseline values]) to enhance performance, once temperature is below the threshold. GDVFS reduces tile temperature by 4◦C atmost whereas HB
& CB reduce it by 3.7◦C and 4.1◦C, respectively for Body16. In case of Freq, these reductions are 2.7◦C by GDVFS, and 3.4◦C & 3◦C for HB & CB, respectively. The memory intensive application, Freq, does not allow much cache shrinking, hence, reduction is lesser than Body16. Figure 6.13 & 6.14 show the change in peak &
average chip temperature for Body16 & Freq, respectively. GDVFS reduces peak temperature by 5◦C for both the applications, but lesser reduction of 2.8◦C &
2.2◦C are noticed for average chip temperature for Body16 & Freq, respectively.
HB & CB, on the other hand, reduce peak temperature by 3.4◦C & 3.7◦C for Body16 and 2.1◦C & 2.3◦C for Freq, respectively. But both HB & CB reduce average chip temperature in the range of 3−4◦C for both the applications and perform comparable to GDVFS.
6.4.4.2 Thermal Stability
To ensure circuit reliability, a stable thermal profile is to be maintained in a CMP. Table 6.3 and 6.4 show the standard deviations for thermal changes in
Chapter 6. DiCeR controls Temperature in a TCMP 145
(a) Tile 7 for Body16 (best case)
(b) Tile 10 for Freq (worst case)
Figure 6.12: Temporal Thermal variation of a tile.
(a) Peak Temperature
(b) Average Temperature
Figure 6.13: Temporal change in Chip Temperature of Body16. (best case)
Chapter 6. DiCeR controls Temperature in a TCMP 146
(a) Peak Temperature
(b) Average Temperature
Figure 6.14: Temporal Change in Chip Temperature of Freq. (worst case) Applications Baseline Greedy DVFS HB CB
Black 0.05 0.79 0.63 0.28
Body 0.11 0.83 0.62 0.19
Freq 0.14 0.77 0.69 0.22
Black4 0.06 0.80 0.64 0.28
Body16 0.07 0.78 0.68 0.24
Freq16 0.06 0.77 0.61 0.20
Swap4 0.16 0.72 0.58 0.27
Gmean 0.08 0.78 0.63 0.24
Table 6.3: Standard deviation for temporal changes in Average Chip Temperature.
peak and average chip temperature for the set of applications we used here. The highest standard deviation values for average temperature are 0.69 for HB, and 0.28 for CB; these respective values are 0.45 and 0.21 in case of peak temperature.
Shutting down of heavily used banks degrades more performance in case of HB, hence, more dynamic cache resizing (by turn-ON-OFF) takes place, which changes thermal profile more frequently than CB. However, this change is less frequent than GDVFS. Due to more frequent changes in V/F settings, GDVFS maintains a standard deviation in the range of 0.72 to 0.83 for average temperature, and
Chapter 6. DiCeR controls Temperature in a TCMP 147 Applications Baseline Greedy DVFS HB CB
Black 0.14 1.92 0.29 0.21
Body 0.25 1.85 0.30 0.16
Freq 0.11 2.17 0.45 0.09
Black4 0.15 2.01 0.28 0.21
Body16 0.13 2.29 0.26 0.21
Freq16 0.07 2.17 0.31 0.16
Swap4 0.24 2.03 0.30 0.18
Gmean 0.14 2.06 0.31 0.17
Table 6.4: Standard deviation for temporal changes in Peak Temperature of the Chip.
1.85 to 2.29 for peak temperature. These values indicate a comparable thermal stability of HB and CB with GDVFS.
6.4.4.3 Spatial Variation
The existing diversities in power consumption across the on-chip components build up the diverse spatial thermal profile of the chip. Figure 6.15 shows the spatial thermal status of the chip for baseline, HB and CB, generated from Hotspot 6.0 [3], while running Body16 application. In comparison with baseline, both HB and CB show certain changes, when banks are turned off. The legends in the figures show the decrement in peak and lowest temperature. Tiles experiencing a bank shutdown have lesser temperature, whereas target banks’ temperature are raised up slightly.
Furthermore, we show the individual tile temperature at some certain point when independently HB, CB and GDVFS are applied. Figure 6.16 shows the change in tile temperature for Body16 while applying the corresponding thermal manage- ment technique. The grey coloured box in this figure for HB and CB indicate that, the tile has a turned off bank and hence, trivially having a noticeable reduction in temperature. GDVFS, on the other hand also reduces temperature in the range of 3−4◦C, which is around 4.4◦C at most in case of CB. The maximum temper- ature reduction for HB is around 4.1◦C. These values claim that, our cache based
Chapter 6. DiCeR controls Temperature in a TCMP 148
Icache Dcache
e FPX
a f dbc
L2 Dcache_1 Icache_1
e_1 FPX_1
a_1 f_1 d_1c_1 b_1
L2_1 Dcache_2 Icache_2
e_2 FPX_2
a_2 f_2 d_2c_2 b_2
L2_2 Dcache_3 Icache_3
e_3 FPX_3
a_3 f_3 d_3c_3 b_3
L2_3 Icache_4
Dcache_4
e_4 FPX_4
a_4 f_4 d_4c_4 b_4
L2_4 Dcache_5 Icache_5
e_5 FPX_5
a_5 f_5 d_5c_5 b_5
L2_5 Dcache_6 Icache_6
e_6 FPX_6
a_6 f_6 d_6c_6 b_6
L2_6 Dcache_7 Icache_7
e_7 FPX_7
a_7 f_7 d_7c_7 b_7
L2_7 Icache_8
Dcache_8
e_8 FPX_8
a_8 f_8 d_8c_8 b_8
L2_8 Dcache_9 Icache_9
e_9 FPX_9
a_9 f_9 d_9c_9 b_9
L2_9 Dcache_10 Icache_10
e_10 FPX_10
a_10 f_10 d_10c_10 b_10
L2_10 Dcache_11 Icache_11
e_11 FPX_11
a_11 f_11 d_11c_11 b_11
L2_11 Icache_12
Dcache_12
e_12 FPX_12
a_12 f_12 d_12c_12 b_12
L2_12 Dcache_13 Icache_13
e_13 FPX_13
a_13 f_13 d_13c_13 b_13
L2_13 Dcache_14 Icache_14
e_14 FPX_14
a_14 f_14 d_14c_14 b_14
L2_14 Dcache_15 Icache_15
e_15 FPX_15
a_15 f_15 d_15c_15 b_15
L2_15 389.16 384.01 378.87 373.73 368.59 363.45 358.31 354.89
(a) Baseline
Icache Dcache
e FPX
a f dbc
L2 Dcache_1 Icache_1
e_1 FPX_1
a_1 f_1 d_1c_1 b_1
L2_1 Dcache_2 Icache_2
e_2 FPX_2
a_2 f_2 d_2c_2 b_2
L2_2 Dcache_3 Icache_3
e_3 FPX_3
a_3 f_3 d_3c_3 b_3
L2_3 Icache_4
Dcache_4
e_4 FPX_4
a_4 f_4 d_4c_4 b_4
L2_4 Dcache_5 Icache_5
e_5 FPX_5
a_5 f_5 d_5c_5 b_5
L2_5 Dcache_6 Icache_6
e_6 FPX_6
a_6 f_6 d_6c_6 b_6
L2_6 Dcache_7 Icache_7
e_7 FPX_7
a_7 f_7 d_7c_7 b_7
L2_7 Icache_8
Dcache_8
e_8 FPX_8
a_8 f_8 d_8c_8 b_8
L2_8 Dcache_9 Icache_9
e_9 FPX_9
a_9 f_9 d_9c_9 b_9
L2_9 Dcache_10 Icache_10
e_10 FPX_10
a_10 f_10 d_10c_10 b_10
L2_10 Dcache_11 Icache_11
e_11 FPX_11
a_11 f_11 d_11c_11 b_11
L2_11 Icache_12
Dcache_12
e_12 FPX_12
a_12 f_12 d_12c_12 b_12
L2_12 Dcache_13 Icache_13
e_13 FPX_13
a_13 f_13 d_13c_13 b_13
L2_13 Dcache_14 Icache_14
e_14 FPX_14
a_14 f_14 d_14c_14 b_14
L2_14 Dcache_15 Icache_15
e_15 FPX_15
a_15 f_15 d_15c_15 b_15
L2_15 386.95 381.35 375.75 370.16 364.56 358.96 353.37 349.64
(b) HB
Icache Dcache
e FPX
a f dbc
L2 Dcache_1 Icache_1
e_1 FPX_1
a_1 f_1 d_1c_1 b_1
L2_1 Dcache_2 Icache_2
e_2 FPX_2
a_2 f_2 d_2c_2 b_2
L2_2 Dcache_3 Icache_3
e_3 FPX_3
a_3 f_3 d_3c_3 b_3
L2_3 Icache_4
Dcache_4
e_4 FPX_4
a_4 f_4 d_4c_4 b_4
L2_4 Dcache_5 Icache_5
e_5 FPX_5
a_5 f_5 d_5c_5 b_5
L2_5 Dcache_6 Icache_6
e_6 FPX_6
a_6 f_6 d_6c_6 b_6
L2_6 Dcache_7 Icache_7
e_7 FPX_7
a_7 f_7 d_7c_7 b_7
L2_7 Icache_8
Dcache_8
e_8 FPX_8
a_8 f_8 d_8c_8 b_8
L2_8 Dcache_9 Icache_9
e_9 FPX_9
a_9 f_9 d_9c_9 b_9
L2_9 Dcache_10 Icache_10
e_10 FPX_10
a_10 f_10 d_10c_10 b_10
L2_10 Dcache_11 Icache_11
e_11 FPX_11
a_11 f_11 d_11c_11 b_11
L2_11 Icache_12
Dcache_12
e_12 FPX_12
a_12 f_12 d_12c_12 b_12
L2_12 Dcache_13 Icache_13
e_13 FPX_13
a_13 f_13 d_13c_13 b_13
L2_13 Dcache_14 Icache_14
e_14 FPX_14
a_14 f_14 d_14c_14 b_14
L2_14 Dcache_15 Icache_15
e_15 FPX_15
a_15 f_15 d_15c_15 b_15
L2_15 385.85 380.47 375.10 369.73 364.35 358.98 353.61 350.03
(c) CB
Figure 6.15: Spatial Thermal variation of the Chip for Body16.
policies play a crucial role in reducing average temperature of a tile comparable with the GDVFS policy.
Chapter 6. DiCeR controls Temperature in a TCMP 149
81.7 82.7 82.3 81.4 82.4 83.5 82.8 82.1 82.6 83.2 83.1 82.0
81.4 81.2 81.3 81.1
78.7 79.2 79.3 78.5 79.3 80.0 79.8 79.1 79.1 80.1 79.9 78.9
78.2 78.2 78.4 78.1 79.8 81.0 78.4 77.4 80.9 79.6 79.7 77.9 78.2 78.9 79.1 80.2
78.7 80.0 80.0 77.6 80.4 79.1 79.9 78.3
80.1 81.7 81.2 78.8 78.6 81.5 81.9 79.4
78.8 78.1 78.3 77.3
Baseline Greedy DVFS P2 P1
HB CB
Baseline Greedy DVFS
Figure 6.16: Change in Average Tile Temperature for Body16.
6.4.4.4 Scalability
To show the scalability of our proposal, we have simulated our idea for a smaller sized 4MB L2 and a larger sized 16MB L2 cache. The size of thermal buffer varies across the total cache size in terms of following:
1. Too much reduction in cache size will affect performance drastically.
2. Smaller sized banks create smaller thermal buffer, having lesser potential for temperature reduction.
Our simulation results further justify the couple of facts stated above. For a 4MB cache, peak and average temperature are reduced by around 2◦C; for 8MB these respective reductions are around 3.5◦C and 3.1◦C for average and peak temper- ature in HB and CB. The maximum reduction is shown in case of 16MB cache, which are around 6◦C for average and 5◦C for peak temperature of the chip, for both HB and CB, respectively. From performance degradation perspective, aver- age IPC degradations for HB and CB are 6.3% and 1.8%, respectively. For 8MB
Chapter 6. DiCeR controls Temperature in a TCMP 150
(a) 4MB
(b) 8MB
(c) 16MB
Figure 6.17: Reduction in Peak Temperature for different cache sizes.
and 16MB caches, these values are lesser than 5% and 4% for HB and negligible for CB. Hence, it can be concluded that larger on-chip caches not only enhance performance, but also can play significant role in on-chip thermal management.
Reduction in peak and average temperature for 4MB, 8MB and 16MB are shown in Figures 6.17 and 6.18, respectively.
Chapter 6. DiCeR controls Temperature in a TCMP 151
(a) 4MB
(b) 8MB
(c) 16MB
Figure 6.18: Reduction in Average Chip Temperature for different cache sizes.