5.4 Experimental Evaluation
5.4.1 Results and Analysis
The proposed policy turns off cache banks up to a limit and then turns off ways from the remaining active banks. We term the policy as “WS”. When the way turn off is implemented in the NT-partition, the policy is termed as “WS NT”.
When the policy attempts to turn off ways from both NT and RT partitions, it is termed as “WS NT RT”. Note that turning off ways from only RT partition will not be able to take advantage of DAM, and hence we do not consider this option.
The proposed policies are compared with baseline tiled CMP and two existing approaches: Drowsy cache [1] and simple bank shutdown. The drowsy cache configurations that have been compared here are DR C1 and DR C2 with having 25% and 50% ways, respectively, are in the normal mode and the remaining ways are in the low-power mode. The simple bank shutdown policy turns off banks depending on their workloads up to a given performance degradation threshold, which is termed as “BSP” (ref. Chapter 4). In our experimental setup we have considered cache with size 4MB. We have experimented with associativity 4-way and 8-way.
Gains in EDP Figure 5.10 shows the normalised EDP values for a 4MB 4-way associative L2 cache. The two drowsy cache configurations DR C1 and DR C2 obtain average EDP savings of 14% and 11%, respectively with respect to the baseline. BSP has average EDP savings of 18%. The proposed architecture saves 21% and 24% average EDP for WS-NT and WS-NT-RT respectively with respect to the baseline.
Static Energy savings The savings obtained in cache leakage energy are shown in Figure 5.11 for various benchmarks. Drowsy cache has savings of 40% and 27%
for DR C1 and DR C2, respectively. BSP saves on average 34% static energy. The proposed technique outperforms BSP and Drowsy by saving on average 44% and 47% for WS NT and WS NT RT, respectively. The turned off cache portions not only save energy rather it can be used to control the effective chip temperature.
Chapter 5. DiCeR with DAM 121 Effect on Higher Associative Caches A 4MB 8-way L2 cache obtains av- erage EDP gains of 33% and 35% with respect to baseline for WS-NT and WS- NT-RT, respectively. The respective static savings for WS-NT and WS-NT-RT are 68% and 70%. Figure 5.12 shows the EDP gains and Figure 5.13 shows the static energy savings for the various benchmark applications. The results have been summarised in Table 5.3.
Figure 5.10: Savings in EDP in comparison with BSP and Drowsy Cache for 4MB 4-way L2.
Figure 5.11: Savings in Static Energy in comparison with BSP and Drowsy Cache for 4MB 4-way L2.
As can be observed the EDP gains in the proposed architecture are more for an 8-way associative cache as compared to a 4-way associative cache of the same size (note that EDP gains for 4-way are around 21−24%). This improvement is achieved as in a higher associative cache we can shutdown more portion of the set belonging for the NT-partition, yet maintaining performance due to associativity
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Figure 5.12: Savings in EDP in comparison with BSP and Drowsy Cache for 4MB 8-way L2.
Figure 5.13: Savings in Static Energy in comparison with BSP and Drowsy Cache for 4MB 8-way L2.
Parameters DR C1 DR C2 BSP WS NT WS NT RT
EDP gains 21% 15% 25% 33% 35%
Static Energy 51% 41% 47% 68% 70%
IPC Degradation 1.15% 1.0% -0.9% 2.1% 2.0%
Table 5.3: Summary of improvement over baseline for a 4MB 8-way set asso- ciative L2 cache.
management. Note that these savings are obtained with IPC degradation of merely 2%.
Effect on Smaller Sized Cache Figure 5.14 shows the EDP savings and Figure 5.15 shows the static energy savings for a 2MB 8 way associative L2 cache.
The EDP savings are around 15% and 17% and static energy savings are 49% and
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Figure 5.14: Normalised EDP gains for 2MB 8-way L2 with re- spect to baseline.
Figure 5.15: Normalised Static Energy values for 2MB 8-way L2 with respect to baseline.
52% for WS NT and WS NT RT, respectively over the baseline. If the cache size is small, the scope for only bank shutdown reduces due to capacity issues, hence the combination of bank and way shutdown helps to save energy. These energy savings are achieved with a IPC degradation of 2.6%, on an average.
Controlling IPC Degradation If an application changes its WSS later during execution, then performance degrades, especially for smaller caches. To rectify this, some of the turned off ways are selectively turned on at runtime from RT and/or NT parts of the banks. Here we get 40% savings in static energy (Figure 5.16) which is slightly lesser than earlier value of 52% as some ways are turned- on. As expected, in this case we are able to maintain performance (Figure 5.17)
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Figure 5.16: Normalised Static Energy values for 2MB 8-way L2 for way-off as well as way turn-on policy.
Figure 5.17: Normalised IPC values for 2MB 8-way L2 for way- off as well as way turn-on policy.
compared to 2.6% degradation in earlier instance.
Overhead The proposed technique requires an additional mapping table to implement CMP-SVR, which leads to area overhead of 9.5% and 1% for power [34]. Power gating circuitry of cache banks and cache ways, used in proposed work, would need negligible circuit overheads, similar to other existing approaches [65]. The cache usage statistics can be maintained by the cache controllers.
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