From the invention of the first point-contact transistor at Bell Labs to the availability of first commercial integrated circuit (IC), people could not anticipate the broad social impact that this invention would produce. The prediction that the integration density, i.e., the number of transistors on an integrated circuit leading to the minimum cost per integrated component, will continue to double every year is proved to be correct not only until 1975 but till today.
The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.
– G. Moore, 1965[1]
The spectacular improvement in circuit complexity and performance is due to the steady decrease in feature size of semiconductor devices. With the advances in lithographic tech- nology, it is possible to manufacture on-chip structures with higher resolution. As a result, the area, speed and power characteristics of transistors improve with scaling in lateral dimen- sions of devices. However, with the widespread use of bipolar devices in the development of ICs, many obstacles preclude the scaling of ICs, e.g., (i) on-chip resistors and diodes make inefficient use of die area, (ii) the speed of bipolar transistors does not scale with the lateral dimensions, (iii) with difficulty in device isolation and inefficient design, power consumption increases, etc. Further, with the maturity in metal oxide semiconductor (MOS) technology, the scaling potential of MOS devices is realized. The compactness of MOS circuits and higher yield capability resulted in dramatic increase in density of devices per IC as compared to bipolar ICs. Alternatively, it can be presumed in an ironic way that the refinement of bipo- lar technology has paved the path to the efficient exploitation of MOS technology and rapid development of high density ICs.
1.1 Evolution in integrated circuit technology and design trends
With seminal advances in fabrication technology, there has been an explosive growth of microelectronics industry. The emergence of new applications has imposed various chal- lenges on principal objectives of designing ICs over the past three decades. Further, these challenges have induced several shifts to the IC design paradigm. The evolution of IC design paradigm is shown in Figure 1.1. In the 1960’s and 1970’s, the primary concern was to maxi- mize yield of such high density ICs by adding the challenges to design more compact circuits and die area. As the electronic systems were made by incorporating more number of ICs, the interconnects were supported by both intra-chip and the board level interconnects. However, as board level interconnects have high latency and dissipate large amounts of power, it lim- its the speed and power performances of the system. This favors the development of higher functionality per silicon area ICs with ensuing reduction in the number of ICs comprising a system. With lower number of ICs, the speed performance of a system became increas- ingly dependent on the speed of IC. Therefore, the development of high speed ICs became a primary design objective by the 1980’s.
1970’s
Ultra−low power Power
Speed/power/noise
Speed/power Area
1980’s 1990’s 2000’s 2010’s
Time
Speed/area Speed
.
Figure 1.1:Evolution of integrated circuit design trend [2]
Meanwhile, due to the emergence of a new class of applications which emphasized on the portable electronic devices, there was a demand to develop ultra-low power ICs, consid- ering power dissipation to be the primary design criterion. Further, with progress in scaling of devices, it is possible to integrate a large number of transistors on a single die with smaller feature lengths and supply voltages. This induces significant economic and technical difficul-
ties on the yield because of increased on-chip power dissipation. By the early 1990, it became clear that there was a growing need of high performance circuits in the semiconductor industry to support the market demand. This directed the design process in 1990’s to focus on devel- oping a number of efficient design approaches for optimizing speed and power of circuits. A series of several lines of commercial microprocessors considering the evolution of power con- sumption is shown in Figure 1.2. Furthermore, increased circuit complexity and aggressive device scaling have imposed several deleterious effects on the development of high speed ICs, such as signal delay uncertainty, on-chip clock jitter, noise margin degradation, etc. As avoid- ing such effects is no longer possible in the design of high speed ICs, it is necessary to shift the design focus towards low power. With the advent of deep-submicron technologies in twenty
1970 1980 1990 2000 2010
1000
100
10
1 10000
Power density (Watt/sq. cm)
Year
Hot plate
Sun surface
Nuclear reactor Rocket nozzle
4004 5006
8080 8085
8086
80286
80386
Pentium pro Pentium II
IV
i3 Itanium 2 i5
Itanium i7
80486
Core 2 Pentium III Duo
Pentium .
Figure 1.2:Evolution of microprocessor power consumption (Intel microprocessor family) [2].
first century, device scaling is continued to keep up with the Moore’s law. Accordingly, the overall power dissipation of a chip continues to increase indeterministically . With increase in on-chip power dissipation, it is evident to come up with new challenging and expensive solutions, such as liquid cooling technologies, which significantly increase the overall cost of the system. Moreover, with explosive growth of portable and handheld devices, mobiles, PDAs, tablets, etc., a technical solution is needed to account for the tradeoff among silicon