7.1 Fabrication of edge reflection type SAW devices on silicon
7.1.2 Fabrication process
The fabrication procedure of the edge reflection type SAW devices on piezoelectric substrates mentioned in [10] is closely followed in this work.
(a) Layout design
The layout of IDT, groove dimensions and ZnO patterns are graphically designed using CleWin software. Three layered design with standard alignment marks is chosen to accomplish the IDT, groove and ZnO pattern layouts without any misalignment. The mask plates are prepared according to the process employed in Chapter 4, Section 4.12(b). The unwanted photo-resist is removed using acetone, followed by piranha cleaning process for 30 s. Microscopic images of IDT mask plate and the magnified view of IDT structure are shown in Fig. 7.1. The major fabrication process steps of three possible processes are shown in Fig. 7.2, Fig. 7.3, and Fig. 7.4 respectively.
(b) Cleaning of wafers
Silicon samples are cleaned using standard piranha cleaning followed by 15 seconds HF dip.
Piranha recipe is prepared with 3:1 ratios of H2SO4 and H2O2 to remove contaminants present in silicon wafers. The samples are dipped HF solution for 30 s to remove the presence of native oxide. Finally, wafers are cleaned with DI water and dried using filtered nitrogen gas.
(a) (b)
Fig. 7.1. (a) Optical microscopic images of IDT structure on mask plate and (b) magnified view of IDT.
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Chapter 7 Fabrication of ER type SAW devices on silicon
Cleaning of Si wafer using piranha cleaning process or
RCA1 and RCA2
UV exposure using MJB4 Wet oxidation process
Cleaning with acetone, IPA, then blow dry
Dehydration bake: 10 minute, 200°C
Photoresist coating:
AZ5142 of 1.2 µm
Development of photoresist using MF 26A Hard bake:
3 minutes, 110°C
Deposition Au/Cr:
100nm/10nm Removal of photoresist:
Acetone & post bake 120°C IDT structure over Si wafer
Si wafer Al metal
Photoresist material
Photoresist after UV exposure Mask
UV light
Photoresist coating of AZ 4562 with 4000 rpm and UV lithography process for DRIE process Annealing of ZnO at 650 °C
Deposition of ZnO using RF sputtering
Proposed edge reflection type SAW devices on silicon after RIE and DRIE process for development of grooves Proposed edge reflection type SAW devices on silicon
with patterned ZnO film developed using hard mask.
Soft bake: 1 minute, 110°C
Fig. 7.2. Fabrication Process flow of ER type SAW devices on silicon with grooves developed at thelast.
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Chapter 7 Fabrication of ER type SAW devices on silicon
Cleaning of Si wafer using piranha cleaning process or
RCA1 and RCA2
UV exposure using MJB4 Wet oxidation process
Cleaning with acetone, IPA, then blow dry
Dehydration bake: 10 minute, 200°C
Photoresist coating: AZ 4562 of 1.2 µm
Development of photoresist using MF 26A Hard bake:
3 minutes, 110°C
Si wafer Al metal
Photoresist material
Photoresist after UV exposure Mask
UV light
Photoresist coating of AZ 5142 with 6000 rpm and UV lithography process for IDT pattern
Proposed edge reflection type SAW devices on silicon after deposition of ZnO using RF sputtering.
Proposed edge reflection type SAW devices on silicon with patterned ZnO film developed using hard mask.
Development of vertical grooves in silicon suing DRIE and RIE process.
Development of IDT pattern after chromium and gold deposition and lift off process.
Soft bake: 1 minute, 110°C
Fig. 7.3. Fabrication Process flow of ER type SAW devices on silicon with grooves developed first IDT.
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Chapter 7 Fabrication of ER type SAW devices on silicon
Cleaning of Si wafer using piranha cleaning process or
RCA1 and RCA2
UV exposure using MJB4 Wet oxidation process
Cleaning with acetone, IPA, then blow dry
Dehydration bake: 10 minute, 200°C
Photoresist coating:
AZ5142 of 1.2 µm
Development of photoresist using MF 26A Hard bake:
3 minutes, 110°C
Deposition Au/Cr:
100nm/10nm Removal of photoresist:
Acetone & post bake 120°C IDT structure over Si wafer
Si wafer Al metal
Photoresist material
Photoresist after UV exposure Mask
UV light
Photoresist coating of AZ 4562 with 4000 rpm and UV lithography process for DRIE process
Proposed edge reflection type SAW devices on silicon after deposition of ZnO using RF sputtering.
Proposed edge reflection type SAW devices on silicon with patterned ZnO film developed using hard mask.
Development of vertical grooves in silicon suing DRIE and RIE process.
Soft bake: 1 minute, 110°C
Fig. 7.4. Fabrication Process flow of ER type SAW devices on silicon with grooves developed after IDT.
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Chapter 7 Fabrication of ER type SAW devices on silicon (c) Oxidation of silicon wafers
2 µm thick oxide layers are obtained on silicon samples through wet oxidation process of duration 11 hr at 1100℃, we obtained oxide layer thicknesses of 2.06 µm on silicon wafers. We propose three possible fabrication processes for ZnO/IDT/Si structured edge reflection type SAW devices.
Fig. 7.2 shows, the efficient process for the development of ER type SAW devices on silicon.
However due to the limited fabrication facilities, we opted for the fabrication process flow detailed in Fig. 7.3, where vertical grooves are developed using UV lithography process followed by DRIE process. Due to the presence of oxide layer, initially RIE process is employed for oxide removal and followed by DRIE process for silicon substrate. The microscopic image of developed grooves in silicon are shown in Fig. 7.5(a). Lithography process is carried out for the IDT pattern, but due to the presence of grooves, the obtained photoresist coating is not uniform due to the edges, as shown in Fig. 7.5(b). Further, the deposition of chromium and gold metals are carried out using RF sputtering and followed by lift process. The microscopic images of obtained IDT
(a) (b)
Fig. 7.5. Microscopic images of vertical grooves developed in silicon substrate and (b) developed IDT photoresist pattern developed using MF-26A solution.
Fig. 7.6. Microscopic images of developed IDT structure after the development of mircomachined grooves.
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Chapter 7 Fabrication of ER type SAW devices on silicon structure are shown in Fig. 7.6. From the microscopic images of IDT structure, we conclude that the fabrication process is not suitable for the fabrication of ER type SAW devices due to the uneven development of photoresist causes improper IDT structure.
As the first process is limited by fabrication facility and second process is practically not possible, we opted for third process (Fig. 7.4) where the development of vertical groove process is carried out after the development of IDT structure. Finally, ZnO is deposited using RF sputtering. The detailed fabrication process steps are as follows.
(d) Photoresist coating
The wafers are spin-coated with positive photoresist for the development of IDT pattern and then placed inside the spin coater. It is ensured that the center of the wafer is exactly aligned with the spin coater. AZ 5142 photoresist (AZ Electronic Materials, UK) is dispensed from the bottle and spread all over the wafer. The wafer spinning program starts with 500 rpm for 5 s, followed by 1000 rpm for 5 s and finally 6000 rpm for 40 s, and the ramp rate of 500 rpm/s is used. By this method, the photoresist thickness around 1.2 µm is achieved over the wafer.
The spun samples with photoresist coating are placed on a hot plate at a temperature of 110°C for 60 s. To avoid wafer getting stuck to the hotplate surface, aluminum foil is placed between wafer and hot plate.
(e) UV exposure for IDT structure
The sample with photoresist coating is placed in MJB4 (SUSS MicroTech) with 2” substrate chuck. The setup parameters such as wedge correction and alignment of substrate are performed manually and exposure is carried out with an optimized UV dosage of 7 seconds.
The exposed samples are developed using MF 26A solution, care has been taken to develop IDT
(a) (b)
Fig. 7.7. (a) Developed IDT structure of a two port resonator and (b) magnified view of IDT structure.
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Chapter 7 Fabrication of ER type SAW devices on silicon structure without over development or under development by constant inspection under microscope. Further, chromium (10 nm) and gold (100 nm) thickness are deposited using RF sputtering process, and the complete sputtering parameters are mentioned in Chapter 4, Section 4.1.2(i). After metallization the samples are kept in acetone for lift off process followed with DI water rinse and dried using nitrogen flush. The microscopic image of obtained IDT structure is shown in Fig. 7.7.
(f) Photoresist coating for DRIE process
The wafers are spin coated with positive photoresist for the development of vertical grooves in silicon pattern. The samples are placed inside the spin coater. It is ensured that the center of the wafer is exactly aligned with the spin coater. AZ 4562 photoresist (AZ electronic chemicals) is dispensed from the bottle and spread all over the wafer. The wafer spinning program starts with 500 rpm for 5 s, followed by 1000 rpm for 5 s and finally 4000 rpm for 40 s, and the ramp rate of 500 rpm/s is used. By this method, the photoresist thickness around 5 µm is achieved over the wafer.
(g) UV exposure for DRIE process
Before UV exposure, the samples with photoresist coating are placed on a hot plate at a temperature of 110°C for 60 s. The setup parameters such as wedge correction and alignment of substrate are performed manually and exposure is carried out with an UV dosage of 14 s finalized after a few trials. The exposed samples are developed using MF 26A solution for 75- 80 s, followed by post baking process at 110°C for 180 s. The microscopic image of obtained groove pattern is shown in Fig. 7.8(a) shows the developed groove pattern with some uncovered metal region. In general, metals are not allowed in the DRIE or RIE process due to contamination issues. So, to overcome this problem, we kept sample in gold etchant (KI:Iodine:DI = 4:1:40) and
(a) (b)
Fig. 7.8. (a) Developed groove structure and (b) removal of unwanted metallic regions.
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Chapter 7 Fabrication of ER type SAW devices on silicon further in chromium etchant to remove the uncovered gold and chromium metal portions. Fig.
7.8(b) shows the removal of unwanted metallic portions of IDT bus bars.
(h) RIE process
Before DRIE process, the oxide layer has been etched using RIE process. The parameters of the RIE process are as follows
RF power: 50 W
Chamber pressure: 5 mTorr Temperature: 0°C
Recipe: CHF3-40
Etching Time: 11 minutes (i) DRIE process
DRIE process is carried out to obtain 80 µm deep vertical grooves in silicon to aid in total reflection of generated surface waves. The etching parameters of the DRIE process are as follows
RF power: 75 W
Chamber pressure: 20 mTorr Temperature: 30°C
Recipe: SF6: C4F8: O2 = 250:150:10 sccm Etching Time: 14 minutes
The microscopic images of the device after the RIE and DRIE processes are shown in Fig. 7.9(a) and (b), respectively.
(a) (b)
Fig. 7.9. (a) Microscopic image of ER device after RIE process (b) ER type device after DRIE process showing the vertically developed groove.
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Chapter 7 Fabrication of ER type SAW devices on silicon (j) ZnO deposition
According to trail run of ZnO deposition at room temperature carried out at IISc, Bangalore, we obtained 278 nm thick ZnO film for 1000 s deposition implying a growth rate of 16.68 nm/minute.
Accordingly we carried out ZnO deposition for 59 mins to obtain 1 µm thickness of ZnO film. The deposition is carried out at room temperature with RF power of 50 W in argon environment with vacuum parameters similar to Table 4.5 in Chapter 4, Section 4.12 (k). The samples are annealed at temperature of 650°C finalized after XRD analysis as mention in Chapter 4, Section 4.12 (l).
Etching of ZnO is carried out according to the ZnO etching process discussed in Chapter 4, Section 4.1.2.