Stability of the OFETs

Contents

Chapter 1 Introduction

1.10. Stability of the OFETs

The stability of the FET devices can be classified into two types (i) Operational stability (ii) environmental stability. OFETs are layered structures consisting of a semiconductor, dielectric, gate electrode, and source/drain electrodes, so each layer as well as the interfaces between the layers plays an important role in the stability. The electrical performance and operational stability of the OFETs are correlated closely with the dielectric surface properties and microstructural order of the organic semiconducting layer as well as with the density of interface traps. The semiconductor, dielectric, and semiconductor/dielectric interface are the most vulnerable sites for charge trapping. The understanding of nature and origin of these traps is significant. The operational stability related to the stability under bias stress. The ambient stability related to the device stability under ambient humidity conditions. Hysteresis is the main cause for the bias

Introduction

stress and device degradation. In the subsequent sections, hysteresis and bias-stress of the devices were discussed.

1.10.1. Hysteresis

OFETs often exhibit a current hysteresis (difference between the forward and the reverse sweeps). The hysteresis effects are very well observed in OFETs and causes instability in the device operation. Hysteresis is essentially the difference in the IDS curves observed during forward and backward sweeping of V_GS of transfer characteristic curves. It could be useful in non-volatile memory devices, but it has to be avoided in standard integrated circuits particularly for display applications. The detailed investigations of hysteresis effects are rare and a complete picture of the physical background that may cause hysteresis in OFETs is still unexplored. Some of the mechanisms causing hysteresis in OFETs are already quite well described in the literature. They are (1) Interface trapped charges (also called interface state) are defects or impurities at the interface that can be charged or discharged (2) Fixed charges in oxide is a positive charge due to structural defects close to the channel (2 nm), which does not communicate with the substrate. (3) Trapped charges in dielectric are electrons or holes trapped in the bulk of the dielectric layer. These traps can be introduced during device fabrication and the charges (electrons or holes) are injected during device operation. (4) Mobile charges in dielectric are mainly small alkali metal cations and H⁺, but can also be larger cations or anions.¹²⁷

Depending on the microscopic effect the “hysteresis” can be classified in to two: (1) Clockwise hysteresis (CH) arises is due to the charge trapping at the interface of dielectric and semiconductor. (2) Anti-clockwise hysteresis (ACH) (Figure 1.12(a), (b)) arises due to (a) Effects of mobile charges close to or in the semiconductor channel near the semiconductor/ dielectric interface. They are (i) Trapped majority or minority charges in the channel close to the semiconductor/dielectric interface (ii) Charge injection from the semiconductor into the dielectric. (iii) Slow reactions (e.g. bipolaron formation) of mobile charge carriers in the polymeric semiconductor. (iv) Mobile ions in the semiconductor.

(b) Effects resulting in a bulk polarization of the gate dielectric. They are (i) Polarization of the dielectric (ferroelectrics as dielectric or meta-stable “quasi-ferroelectric”

polarization in the dielectric) (ii) Mobile ions in the dielectric (iii) Charge injection from the gate electrode into the dielectric.

Chapter 1

Figure 1.12. Schematic representation of hysteresis (a) Clockwise hysteresis (b) Anti-clockwise hysteresis (c) Bias-stress effect and (d) Anomalous bias-stress effect.

1.10.2. Bias-stress effect

Bias-stress is the application of constant V_DS and V_GS for an extended period of time.

Moreover, we often have a persistent shift of the transfer characteristic when a gate bias is applied for a prolonged time. These phenomena are known as electrical instability or bias- stress effects. Electrical instability is most likely caused by the trapping of charge in long- lived trap states in the device layers. The term “long-lived” refers to a trapping and release time, which is long compared to the time needed to measure a transfer characteristic. Hysteresis and bias-stress IDS degradation might have the same physical origin.¹²⁸

Depending on the variation of IDS with time, bias-stress effects are classified in to two types. They are (1) bias-stress effect and (2) anomalous bias-stress effect. These are shown in the Figure 1.12 (c) and (d). The bias-stress effect is due to the charge trapping at the interface and anomalous bias stress is due to the slow polarization of the gate dielectric or charge injection from the gate electrode. Under bias-stress the direction of the threshold voltage shift is such that a fully turned on OFET slowly turns itself off and vice versa under bias-stress. Investigating the bias-stress in an OFET can also cause a

Introduction

change in effective field-effect mobility, which is attributed to an irreversible structural change in the semiconductor due to the electro-strictive effect.¹²⁹

Based on the above literature in this thesis the second, third chapters gives the detailed study of the structure property relationship in n-type semiconducting materials based on Perylenediimide and Naphthalenediimide by fabricating the bottom gate top contact organic field-effect transistors. Fourth chapter describes the effect of dielectric material, surface assembled monolayer and channel length on the performance of OFET based on perylene diimide molecule. Finally, an ambipolar organic field effect transistor fabricated on low cost Al foil gate substrate which operates at a very low voltage is presented in the last chapter.