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International Journal of Electrical, Electronics and Computer Systems (IJEECS)

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ISSN (Online): 2347-2820, Volume -3, Issue-9 2015 57

Combating Power and Latency Using C-Element with Security System

1Suman Sekhar, ² Deepak Kumar Naik, ³MKS. Uthaya Kumar, ⁴K. SatishKumar, ⁵ D.Arun Kumar

1,2 Professor, ³Associate Professor,^4,5 Assistant Professor, Dept. of E.C.E., P.I.T.S., Ongole,

Abstract: This research mainly concentrates on design of low power and more secured memory organization. The flip-flop replacement without timing and placement capacity restraint violation becomes a quite complex problem. To deal with the intricacy effectively, this paper proposes several techniques. First, it achieves a co-ordinate transformation to identify those flip flops that can be combined and their legal regions. It shows how to build a combination table to specify possible combinations of flip- flops provided by a library. Finally, a hierarchical way is designed merge flip-flops with more security using Scalable Encryption Algorithm (SEA). Besides power reduction, the objective of reducing the total wire length is also achieved.

Keywords– Merge Flip-Flops, Co-Ordinate Transformation, Combination Table, Latency.

I. INTRODUCTION

Design involving significant less area-delay and power- delay complexities has been proposed in Montgomery Multiplier for Finite Field [1]. In [2] the proposed digit- serial design was being used for “Almost equally spaced polynomial” AESP-based fields with the same digit-size as the case of trinomial-based fields with a small increase in area.

Centralized elastic bubble router - a router micro- architecture based on the use of centralized buffers (CB) with elastic buffered (EB) links. At low loads, the CB is power gated, bypassed, and optimized to produce single cycle operation [3].

Low latency and low power consumption is presented as a hybrid scheme in [4] with virtual circuit switching, has been proposed to intermingle with circuit switching and packet switching.

CMOS technology widen, the driving capability of an inverter-based clock buffer increases extremely. The driving capability of a clock buffer can be evaluated by the number of minimum-sized inverters that it can drive on a given rising or falling time. However, the locations of some flip-flops would be changed after this replacement, thus the wire-lengths of net connecting pins to a flip-flop are also changed. To avoid violating the timing constraints, we modify the wire-lengths of net connecting pins to a flip-flop cannot be longer than specified values after this process. To guarantee that a new flip-flop can be placed within the desired region, we also need to consider the area capacity of the region.

We divide the whole placement region into several bins,

and each bin has an area capacity denoting the remaining area that additional cells can be placed within it.

II. MEMORY ORGANIZATION

Memory organization is two-fold. First we discuss the hardware (physical) organization, then the internal architecture. The type of computer and its size do not reflect the type of memories that the computer uses.

Some computers have a mixture of memory types. For example, they may use some type of magnetic memory (core or film) and also a semiconductor memory (static or dynamic).

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…(2) Input Buffer:

The Input buffer is also commonly known as the input area or input block. When referring to computer memory, the input buffer is a location that holds all incoming information before it continues to the CPU for processing. Input buffer can be also used to describe various other hardware or software buffers used to store information before it is processed. Memory Block:

Random-access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits.

Ring Counter

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. Loading binary 1000 into the ring counter, above, prior to shifting yields a viewable pattern. The data pattern for a single stage repeats every four clock pulses in our 4-stage example.

The waveforms for all four stages look the same, except

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for the one clock time delay from one stage to the next as shown in Fig.2.

Existing system

In [6] a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC.

The discussions in [7] proposed a combination scheme for NoCs, which aims at gaining low latency and low power consumption. In the presented combination scheme, a peculiar switching mechanism, called virtual circuit switching, is proposed to interweave with circuit switching and packet switching.

Proposed System

Fig.2. Proposed System.

Gated Driver Tree: Gated driver tree derived from the same clock gating signals of the blocks that they drive.

Thus, in a quad-tree clock distribution network, the

“gate” signal of the gate driver at the level (CKE) should be asserted when the active DET flip-flop.

III. MODIFIED RING COUNTER

A. DET (Double Edge Triggered) Flip-Flops

Double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half the logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels the clock, is analyzed and a new circuit design of CMOS DET In this paper, we propose to use double-edge-triggered (DET) flip-flops instead of traditional DFFs in the ring counter to halve the operating clock frequency as shown in Fig.3.

Fig.3. Modified Ring Counter.

C-Element

The Muller C-element, or Muller C-gate, is a commonly used asynchronous logic component originally designed by David E. Muller. It applies logical operations on the inputs and has

C. SEA

Most present symmetric encryption algorithms result from a trade-off between implementation cost and resulting performances. In addition, they generally aim to be implemented efficiently on a large variety of platforms. In this paper, we take an opposite approach and consider a context where we have very limited processing resources and throughput requirements. For this purpose, we propose low-cost encryption routines (i.e. with small code size and memory) targeted for processors with a limited instruction set (i.e. AND, OR, XOR gates, word rotation and modular addition). The proposed design is parametric in the text, key and processor size, allows efficient combination of encryption/decryption, “on-the-fly” key derivation and its security against a number of recent cryptanalytic techniques is discussed. Target applications for such routines include any context requiring low-cost encryption and/or authentication.

IV. SPECIFICATIONS

A. Parameters and Definitions

SEA n, b operates on various text, key and word sizes. It is based on a Feistel structure with a variable number of rounds, and is defined with respect to the following parameters:

n: plaintext size, key size.

b: processor (or word) size nb = n

2b: number of words per Feistel branch.

nr: number of block cipher rounds.

As only constraint, it is required that n is a multiple of 6b. For example, using an 8-bit processor, we can derive 48, 96, 144, …-bit block ciphers, respectively denoted as SEA48,8, SEA 96,8, SEA 144,8, ... Let x be a n2-bit vector. In the following, we will consider two representations:

Bit Representation:

…(3) Word Representation:

…(4) B. Basic Operation

Due to the simplicity constrains, SEAn, b is based on limited number of elementary operations (selected for their availability in any processing device) denoted as follows: 1) bitwise XOR ; 2) addition mod 2b;

3)substitution box S.

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C. Round and Key Round

Definitions of the terminologies are as follows encrypt round FE, decrypt round FD, and key round FK.

V. RESULTS

Results of this paper is as shown in bellow Figs.5 to 7.

VI. CONCLUSION

Finally, this proposed algorithm for flip-flop replacement with power reduction is presented digital

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integrated circuit design. The procedure of flip-flop replacements is based on the combination table, which records the relationships among the flip-flop types. The technique of pseudo type is developed to make and enumerate all possible combinations in the combination table. By taking necessary decisions of replacements from the combination table, the impossible combinations of flip -flops not be considered that reduce execution time. Besides power reduction, the objective of minimizing the total wirelength and providing security using SEA is also be considered to the cost, security function. The experimental results display that our algorithm can achieve a balance between power reduction and wire length reduction.

REFERENCES

[1] Xie, J., jun He, J., & Meher, P. K. (2013). Low latency systolic montgomery multiplier for finite

field $ GF (2^{m}) based on

pentanomials. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(2), 385- 389.

[2] Pan, J. S., Lee, C. Y., & Meher, P. K. (2013).

Low-latency digit-serial and digit-parallel systolic multipliers for large binary extension

fields. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(12), 3195-3204.

[3] Hassan, S. M., & Yalamanchili, S. (2013, April).

Centralized buffer router: A low latency, low power router for high radix nocs. In Networks on Chip (NoCS), 2013 Seventh IEEE/ACM International Symposium on (pp. 1-8). IEEE.

[4] Jiang, G., Li, Z., Wang, F., & Wei, S. (2015). A low-latency and low-power hybrid scheme for on-chip networks. IEEE Transactions on very large scale Integration (VLSI) Systems, 23(4), 664-677.

[5] Shenbagavalli, S., & Karthikeyan, S. (2015, November). An efficient low power noc router architecture design. In Green Engineering and Technologies (IC-GET), 2015 Online International Conference on (pp. 1-8). IEEE.

[6] Lee, T. Y., & Huang, C. H. (2014). Design of smart power-saving architecture for network on chip. VLSI Design, 2014, 7.

[7] Bhagat, A. V., Sayankar, B. B., & Agrawal, P.

Minimization of Latency and Power for Network-on-Chip.

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