transition interleaved boost converter
M. Rezvanyvardom E. Adib H. Farzanehfard M. Mohammadi
Department of Electrical Engineering, Isfahan University of Technology, Isfahan, Iran E-mail: [email protected]
Abstract:In this study, a new interleaved zero-current transition pulse-width modulation (PWM) boost converter, which uses only one auxiliary switch to provide soft-switching condition is presented and analysed. In order to reduce switching losses and to obtain high efficiency, a non-dissipative soft-switching cell is used. In the proposed interleaved converter, soft switching is obtained for all semiconductor devices. The main and auxiliary switches turn on and off under zero-current condition. Thus, the reverse-recovery losses of boost diodes are reduced and also, high efficiency is achieved owing to reduction of switching losses. Also, implementation of control circuit is simple since the proposed circuit is controlled by PWM method. Operating principles, theoretical analysis, the design procedure along with a design example are described and verified experimentally. Experimental results are presented to justify the validity of theoretical analysis.
1 Introduction
Current fed DC – DC converters are widely employed in industrial applications. Nowadays, more and more renewable energy sources are applied, but, most of these sources, such as fuel cells and solar cells provide low and unregulated output voltage [1 – 4]. Therefore for renewable power sources, high efficiency and high step-up DC – DC converters are necessary as an interface circuit. This interface circuit should absorb power from a low-voltage high-current source and provide a high DC voltage for load which is usually an inverter. Thus, the voltage should be boosted and regulated by using current fed converters as the interface circuit. When power rating increases, it is needed to connect converters in parallel to provide the output power. The interleaved structure is used in high-current and high-power applications because of its advantages such as power distribution and reduction of input current ripple as well as reduction of passive components and the electro- magnetic interference (EMI) filter size [5 – 7]. When isolation is not necessary, boost converter is applied for the interface circuit because of its simple structure. Also, the boost converter is widely applied in single-phase power factor correction circuits[8], because of its continuous input current. In modern DC – DC converters, in order to reduce size and weight, switching frequency is increased [9].
However, high switching frequency will result in high switching losses and increased EMI. Therefore at high switching frequency, soft switching techniques such as zero-voltage transition (ZVT) and zero-current transition (ZCT) are applied to reduce switching losses and increase efficiency. These techniques provide soft switching condition while the control circuit remains PWM. Therefore switching losses and EMI are reduced. By operating under
soft switching condition, DC – DC converters can be applied at higher switching frequency to further reduce the converter size and weight [10 – 18]. ZVT interleaved converters are proper techniques when MOSFET switches are used to reduce capacitive turn on losses as well as switching losses [19 – 21]. For higher power applications where isolated-gate bipolar transistor switches are used owing to their lower conduction losses and cost, ZCT techniques are preferred to eliminate tailing current losses.
Several interleaved ZCT PWM converters are introduced in [22 – 26]. In [22], two auxiliary switches are used to provide soft switching conditions. The current peak of semiconductor devices in the converter introduced in[23]is high although interleaved technique is used. In addition, di/
dt is higher than the proposed interleaved boost converter, which results in higher EMI. In[24, 25], the main switches are turned on under the ZCT condition, but are turned off under the hard-switching condition. In this paper, a new interleaved ZCT PWM converter is introduced, which uses only one auxiliary switch. Furthermore, in this converter the current stresses of the main switches are low. Fig. 1shows proposed interleaved ZCT boost converter. The main converter is composed of D1,D2,S1andS2. The auxiliary circuit is composed of Sa, Lr, Cr, LS1, LS2, Dp1 and Dp2. The intrinsic anti-parallel diodes of main switches are DS1
andDS2. The output capacitance and load resistance are Co
andRo, respectively. The proposed converter operates like a conventional interleaved boost converter except during switching instances. Lr and Cr are resonant components, while Sa controls the resonant instant. LS1 and LS2 are snubber inductors of main switches. Auxiliary switch Sa is a unidirectional switch, whereas main switches are bidirectional switches. Complexity of a soft switching converter is determined by additional switches used because
each additional switch requires an additional gate drive signal which would increase the complexity of control circuit as well as the power stage. The proposed converter uses only one additional switch to provide soft switching condition for the main switches. Therefore this circuit has less complexity in comparison with the mentioned converters in the references.
Also, it is important to notice that since the auxiliary circuit elements are not in the main power path, the current rating of auxiliary circuit elements is low.
2 Proposed ZCT PWM interleaved boost converters
In order to simplify the converter analysis, following assumptions are considered:
1. Output capacitor is large enough so that it can be replaced by a DC-voltage source.
2. InductancesL1andL2are equal (L1¼L2).
3. All semiconductor devices are ideal.
To simplify the analysis, L1, L2 and Co are replaced by current and voltage sources, respectively, as shown inFig. 2.
It is important to notice that sources such as fuel cells, batteries and solar panels have low-output voltage level of about 48 V. Hence an efficient high step-up converter such as proposed interleaved boost converter is useful as the interface circuit. The converter operation consists of two symmetrical half cycles during each switching period.
Therefore only half of a switching cycle is explained. In addition, it is assumed that converter operates at steady state.
Converter operation in half of the switching cycle can be divided into nine modes. The equivalent circuit for each operating mode and theoretical waveforms are illustrated in Figs. 3 and 4, respectively. The photograph of the original set-up is shown in the Fig. 5. Before the first mode it is assumed that main switchS1and auxiliary switchSaare off and main switch S2 is conducting L2 current. Also, D1 is conducting and Cris charged toVo.
2.1 Mode 1: [t02t1] (Fig. 2a)
This mode begins by turningS1on. Owing toL1, main switch S1is turned on under zero-current switching (ZCS) condition.
Therefore the current flowing throughS1increases linearly to L1current (Iin) andLS1current decreases linearly fromIinto zero. At the end of this mode, S1 current and LS1 current areIinand zero, respectively. Duration of this mode is
t1−t0=LS1Iin
V0 (1)
whereVois the output voltage andIinis the current ofL1and L2in the proposed converter.
2.2 Mode 2: [t12t2] (Fig. 2b)
Att1, current of resonant inductanceLs1becomes zero. In this modeS1andS2are on andL1andL2are being charged.
Fig. 1 Proposed interleaved ZCS boost converter
Fig. 2 Equivalent circuit of interleaved ZCS boost converter
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Fig. 3 Equivalent circuit of each operating mode a Mode 1
b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9
2.3 Mode 3: [t22t3] (Fig. 2c)
This mode begins by turningSaon to provide soft-switching forS2turn off. By turningSaon, a resonant starts betweenLr
and Cr. Therefore auxiliary switch Sa turns on under ZCS condition. This mode ends when the Cr voltage reaches zero. Duration of this mode is
t3−t2=Tr
2 (2)
whereTris the resonance period ofLrandCr. The voltage on
Crand the current through the auxiliary switch are obtained as VCr(t)=Vocos(v1(t−t2)) (3)
ISa(t)=Vo
Z1sin(v1(t−t2)) (4) wherev1=1/
LrCr
,Z1 =
Lr/Cr
andTr =2p
LrCr
.
In the equation,v1andZ1are the resonant frequency and resonant impedance, respectively.
Fig. 4 Theoretical waveforms of the proposed interleaved converter
Fig. 5 Proposed converter with experimental values
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1 r 1
VCr(t)= − Vo 1+(2Lr/LS1)
sin(veq(t−t3)) (7)
where veq and Leq are the resonant frequency and equal inductance in this mode, respectively, and are obtained from the following equations
veq=1/
LeqCr
and Leq=Lr|LS1|LS2
As theDp1andDp2are the conducting, the voltage onD1and D2increase asVCrdecreases.
VD1(t)=VD2(t)
=Vo+ Vo 1+(2Lr/LS1)
sin(veq(t−t3)) (8)
2.5 Mode 5: [t42t5] (Fig. 2e)
Att4, the currents through main switchesS1andS2reach zero.
Thus anti-parallel diodesDS1andDS2begin to conduct. This mode ends when the current through auxiliary switch Sa
reaches zero at t5. VCr, IS1, IS2, VD1, VD2 and ISa can be calculated using (5) – (8).
2.6 Mode 6: [t52t6] (Fig. 2f)
At t5, the current of auxiliary switch reaches zero. Thus, auxiliary switch Saturns off under ZCS condition. Sum of Dp1 and Dp2 currents run through Crand thus, the voltage across Cr increases. At the end of this mode anti-parallel diodesDS1andDS2turn off. During this modeS2is turned off under ZCS condition.
2.7 Mode 7: [t62t7] (Fig. 2g)
Att6, the anti-parallel diodes DS1andDS2turn off. In this mode, the current through LS2 and Dp2 is constant and equal to Iin. Also, the resonance between LS1 and Cr
continues and the current through LS1 and Dp1 decreases and thus, the current through main switch S1 increases. At the end of this mode the current through LS1 and Dp1
reaches zero and the current ofS1increases toIin.
the proposed converter behaves like a regular interleaved PWM boost converter.
3 Design procedure
This section presents design procedure for the proposed converter.
The converter specifications for 250 W converter are
† Output powerPo¼250 W;
† Output voltageVo¼200 V;
† Input voltageVin¼48 V;
† Switching frequency of the main switchesfsm¼100 kHz;
† Switching frequency of the auxiliary switch fSa¼200 kHz.
The converter specifications for 50 W converter are
† Output powerPo¼50 W;
† Output voltageVo¼200 V;
† Input voltageVin¼48 V;
† Switching frequency of the main switchesfsm¼100 kHz;
† Switching frequency of the auxiliary switch fSa¼200 kHz.
The design procedure of this converter is explained in four steps as following.
3.1 Resonant elements (Cr, Lr, LS1and LS2)
In order to obtain soft switching condition for both main switches, the maximum current through each snubber inductor should be greater thanIinin the fifth mode. In this condition, the current through the main switches will be negative and the main switches body diodes will conduct.
Considering 20% over design, the following relation is obtained
Leq Ls
Vo
Z1=1.2Iin (10) where
Iin= Po
2Vin (11)
Iin= Po
2Vin⇒ILr =Vo
Zr =2.4Iin⇒Zr= Vo
2.4Iin (12) where Po is the output power. Also, the resonant period should be negligible in comparison with the switching
period. Thus, the resonant frequency is selected at least ten times greater than the switching frequency.
Tres=2p CrLr
≥Tsw
10 (13)
where TresandTsware the resonance and switching periods, respectively.
By using (12) and (13), Tres,LrandCr can be obtained.
Before turning the main switches off, the auxiliary circuit should operate to reduce the current through the main switches to zero. Therefore converter minimum duty cycle is Fig. 6 Voltage (top waveform) and current (bottom waveform) of main switch
Voltage scale is 100 V/div, current scale is 3 A/div and time scale is 2.5ms/div
Fig. 7 Voltage (top waveform) and current (bottom waveform) of the auxiliary switch Voltage scale is 100 V/div, current scale is 3 A/div and time scale is 1ms/div
Fig. 8 Voltage of resonant capacitor Cr. Voltage scale is 100 V/div and time scale is 0.5ms/div
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Dmin=t5−t3
Tsw =p−sin−1((2Zr/Vo)Iin)
vrTsw (14) whereLS1andLS2are the snubber inductors of main switches and their value can be calculated like any snubber inductor.
By calculatingLsvalue and using (10) – (13),Tres,LrandCr
can be obtained.
3.2 Selection of S1, S2and Sa
The peak current and voltage stresses of switches are obtained from the following equations
VS1,2=VSa=Vo max (15)
Fig. 9 Voltage (top waveform) and current (bottom waveform) of main switch Voltage scale is 80 V/div, current scale is 0.5 A/div and time scale is 1ms/div
Fig. 10 Voltage (top waveform) and current (bottom waveform) of the auxiliary switch Voltage scale is 80 V/div, current scale is 0.5 A/div and time scale is 1ms/div
Fig. 11 Efficiency versus output power of the proposed interleaved boost converter and its hard switching counterpart
Isw1,2= Po 2Vin+DIL
2 (16)
ISa=Vo
Z1 (17)
whereDILis the current ripple of each input inductor.
3.3 Selection of D1, D2and Do
The current peak and voltage stresses of the diodes are obtained from the following equations
VD1,2 max=2Vo max (18)
VDp1,Dp2 max=Vo max (19) ID1,2 max= Po
2Vin+DIL
2 (20)
ID1,D2 max=Po
Vin+DIL (21) 3.4 Selection of L1, L2 and Co
The value of inductancesL1andL2and capacitance value of Co can be obtained exactly like a conventional PWM converter[27].
4 Experimental results
The schematic of the prototype converter is shown inFig. 6 and the experimental results of the proposed converter topology are shown in Fig. 7. Also the photograph of the original set-up is shown in Fig. 5 that shows the main and control circuit prototypes. The proposed ZCT interleaved boost converter is implemented for input voltage of Vin¼48 VDC and output voltage of Vo¼200 VDC
operating at fsw¼100 kHz. In the implemented prototype, IRGBC20U is used as main and auxiliary switches.
MUR860 diodes are used as D1 and D2 and MUR460 diodes are used as Dp1 and Dp2. A 10 nF and a 100mF capacitors are used as Cr and Co, respectively. Inductors values for L1andL2are 300mH, and Lris 8mH. Inductors values for LS1and LS2 are 16mH. Figs. 7 and 8show the current and voltage waveform of the main and auxiliary switches, respectively, for 250 W converter. The resonant capacitor voltage is presented in Fig. 9. Also, Figs. 10 and 11 show the current and voltage waveform of the main and auxiliary switches, respectively, for 50 W converter. It can be observed that the main switch is turned on under ZCS condition for both converters. Also for both converters, the main switch current is reduced to zero just before turning this switch off. In addition, ZCS is achieved for the auxiliary switch at turn on and turn off instants. Fig. 12 shows the efficiency against output power for the proposed interleaved boost converter and its hard-switching counterpart. The losses of each semiconductor device in the proposed converter and hard-switching converter are compared in Table 1. Table 1 shows detail comparison between the simulation results of the proposed converter and the traditional hard-switched counterpart. The hard- Fig. 12 Photograph of the original setup
Fig. 13 Schematic of control circuit of the proposed interleaved boost converter
Tl494 IC is applied for PWM controller. Also, 74123 IC is used as monostable. The delay circuit is implemented using RC circuits. Also, ICL7667 is applied as gate driver
Table 1 Power losses of each semiconductor device D1or D2
losses
Dp1or Dp2
losses
Auxiliary switch losses
Each main switch losses
Output power
1.2 W 0.3 W 1.5 W 1.8 W 150 W proposed
converter
1.3 W 0.4 W 1.6 W 2.1 W 250 W
2 W 4.2 W 150 W hard
switching converter
2.8 W 5.4 W 250 W
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introduced. This converter uses only one auxiliary switch to provide soft-switching condition for the main and auxiliary switches. The main and auxiliary switches turn on and off under zero-current switching condition. This converter has higher efficiency than the conventional PWM hard- switching converter because of the reduced reverse-recovery losses of boost diodes and switching losses. Also, the proposed converter is controlled by PWM method.
According to the experimental results, the efficiency is improved by about 2.9%. This converter is analysed and the design procedure is presented. The presented experimental results verify the theoretical analysis.
6 References
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