Modeling and Simulation of Negative Capacitance MOSFETs

For this purpose, we used the BSIM-CMG Verilog A model and appropriately modified the model to include the effect of negative capacitance ferroelectric capacitance in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can indeed provide a subthreshold swing of less than 60 mV/dec.

Subthreshold swing

In this report, we explore the idea of negative capacitance in the gate stack of MOSFETs to overcome the Boltzmann limit (SB = 60 mV/dec) and realize low-power high-frequency devices. Much effort has been put into optimizing the electrostatics to keep the unity to a minimum so that the value is reasonably close to 60 mV/dec.

Negative capacitance in ferroelectrics

Origin of permanent polarization in ferroelectrics

Origin of negative capacitance effect

However, if the dipoles are oriented in the negative direction, the local electric field at a dipole can become smaller asEloc =Eext− P0 +γP3. Since γ≈10 [5] in ferroelectrics, a negative polarization along the surface would stabilize the system by reducing the local electric field.

Thesis objective

Therefore, applying a positive electric field can result in negative surface charges, indicating negative capacitance. The origin of negative capacitance is also often discussed in connection with the thermodynamic system.

Organization of the thesis

In this chapter we review the latest achievements in negative capacitance FETs. We begin with a review of the development of the idea of the NC MOSFETs and their future prospects in a theoretical perspective. Finally, we review recent developments in modeling NCFETs with additional physical effects such as ferroelectric multidomain character and leakage in ferroelectrics.

Development and prospects of NCFETs

They showed that for stable operation the total capacitance of the system should be positive, and thus CS−1(Q) > Cins−1(Q) throughout the device's operating region. For ferroelectric FET operating in a stable region, they showed that the minimum subthreshold swing is given by. This is fulfilled only for the doping concentration of NA2 and therefore it would work in hysteresis-free mode [6].

In particular, the hanging gate nanoelectromechanical switch (NEMS) can also cause the negative capacitance effect. As the hanging gate charges, it is attracted towards the MOSFET and as a result the voltage across it decreases. The NEMS switch can then be used in series with the ferroelectric capacitor to obtain an ideal logic switch with SS = 0 mV/dec.

Figure 2.2: Stable operation of NCFETs requires C S −1 (Q) > C ins −1 (Q). This is satisfied only for the doping concentration of N A2 and hence it would be operating in hysterisis free mode [6]

Experimental evidence of NCFETs

Modeling NCFETs

In this work, the core BSIM-CMG model is extended with an additional term vF E =−(a0qch+b0qch3 +c0qch5 ) so that it becomes. 2.5) where normalized mobile and total charges are specified for different geometries of multigate FETs. The resistor provides an additional path to provide screening charges to ferroelectric attenuation of its performance. Multidomain nature of ferroelectrics is considered in [14] where NEGF formalism was used to get the device characteristics.

Higher values of κ are shown to make the ferroelectric polarization more uniform and even the MFIS structure tends to become MFMIS structure. First, we present a compact model that we integrate with the industry standard BSIM-CMG model to study negative capacitance-based FinFETs. We observe a subthreshold swing of less than 60 mV/dec and a negative output conductance in this study.

Figure 2.6: Performance of different NCFETs (a) In lumped NCFET the ferroelectric capacitor can be considered a separate series element (b) In distributed model, KVL and LK equations need to be solved self consistently at each point along ferroelectric and

NCFET analysis using compact models

Results and analysis

An increase in the drain voltage VDS leads to a decrease in the total gate charge due to drain-to-channel coupling modeled by the capacitor CD. An increase in the ferroelectric voltage obviously leads to a decrease in the internal gate voltage, which decreases the channel current. As a result, a lower drain voltage better provides more current in the subthreshold region, especially at larger ferroelectric thicknesses.

A positive feedback mechanism is thus created, which is eventually terminated by the nonlinearities of the ferroelectrics and the internal MOSFET. In summary, we have seen that the addition of a ferroelectric can improve the subthreshold oscillation of the device. Increasing the ferroelectric thickness can lead to better performance, however increasing the thickness can lead to the appearance of hysteresis, which can lead to difficulties in circuit design.

Figure 3.2: Structure of negative capacitance MOSFETs. (a) Actual FinFET structure with an intermediate metal layer (b) Simulated structure which uses a 1D model for the ferroelectric capacitor with charge coupling between the devices.

Modeling double gate ferroelectric MOSFETs

Basic model for double gate MOSFETs

The model result shows that, as expected, the device current increases with increasing ferroelectric thickness. In this chapter, we will look at the operation of NC devices, especially the inverter and the ring oscillator. Finally, we will look at the transient behavior of NC devices with TCAD analysis.

Figure 3.8: Double gate MOSFET device performance. (a) Linear regime (b) Saturation regime I ON increases with increasing ferroelectric thickness

Circuit performance of NC devices

Ring oscillator performance

The increase in period is purely attributed to increase in parasitic capacitance at the output node of an inverter. Due to the addition of a ferroelectric in the gate stack of the ring oscillator, the effective capacitance seen by the previous converter is. 4.2) Since CF E <0 for certain bias conditions, Cef f is actually more that CG increases the delay of the converter.

In this case, in addition to increasing the load capacitance, the polarization itself takes time to change its value. However, it has been observed experimentally [21] that the ring oscillator performance of NCFET is on par with normal FinFET.

Figure 4.1: Infinitely fast switching ferroelectric (ρ = 0). Blue waveform indicates the waveform without ferroelectric, while the red waveform shows the RO characteristics with ferroelectric

Inverter performance

Scalability of NCFETs

The ferroelectric was treated as 1D and externally coupled to the device mentioned in the previous section using the 1D LK equations. Models were considered to account for phenomena such as high field saturation, mobility dependence on doping, band gap narrowing due to high concentration, and mobility degradation due to normal electric fields. As can be seen from the characteristics, the subthreshold oscillation of 5nm technology is almost the same as 7nm technology, while the subthreshold oscillation of 7nm technology with FE is the same as 10nm technology.

This clearly shows that device scaling can proceed using FE technology to reduce device dimensions in accordance with Moore's law without significant short-channel effects. A similar plot is also shown for the input characteristics in the linear regime, where we observe that the sub-threshold oscillations of the FE devices are greatly reduced due to voltage amplification by the negative capacitance ferroelectric. However, as previously discussed, the NC dielectric provides a negative DIBL effect which effectively tends to reduce the threshold voltage at higher discharge voltages and thus reduces the turn-off current and at the same time increases the turn-on current.

Table 4.1: Device dimensions for various technology nodes

Quasistationary anlysis using time domain LK equation

Although the inverter and ring oscillator can be operated at a lower voltage due to the increased subthreshold swing, they have significant disadvantages of operating at a lower speed due to the increased capacitances at the output node. We see that the NC effect indeed provides an immunity to short-channel effects and allows further device scaling. Finally a model is developed using the time-dependent LK equations to obtain quasi-stationary response of 3D FinFET for 7 nm technology node.

In this chapter we develop and study some models that take into account the multidomain nature of the ferroelectrics. This is important as most of the times ferroelectrics are observed to divide into domains to minimize the electrostatic energy due to depolarization fields. We then investigate the performance of short-channel dual-gate MOSFET considering domain interactions.

Figure 4.9: Hysteresis due to large t F E

Time dependent Landau Ginzburg theory with multi do- main ferroelectrics

Analysis with different coupling coefficients

To obtain the initial state of the capacitor, we first assume a random polarization state and allow the Landau Ginzburg free energy to be minimized. Note the sharp drop in vF E as the entire ferroelectric must pass the transition from the negative capacitance regime. In this case, the drop in vF E is smoother since all of the ferroelectric must pass through the process.

However, there is an additional charge that must be supplied by the battery for moving the domain wall. As a result, the battery must provide even less charge, further reducing the negative capacity effect. The smaller negative capacitance is observed as a smaller fraction of the ferroelectric needs to switch. The load associated with domain wall motion is also small.

Figure 5.2: Ferroelectric in series with resistor. Homogeneous ferroelectric is assumed

Double gate MOSFET model with multi domain ferro- electricelectric

Simulation methodology

Results and discussion

The decrease in drain and subsequent subthreshold swing can be justified due to the influence of drain side polarization on source side polarization. Since the drain side polarization is negative, it reduces the polarization at the source side which increases the source side barrier, which reduces the down current. With increase inκp, as source polarization decreases, the depolarization field increases which further increases the source side barrier.

As a result, as the drain voltage increases, the source-side polarization decreases while the drain-side polarization also decreases. This leads to steady voltage drop near the source side making the impedance almost constant. First we have considered a 2D analysis of the ferroelectric capacitor with series resistors and then we have developed a TCAD-based model using which we have analyzed the influence of domain interactions on the NCFET performance.

Figure 5.9: Input characteristics for various κ p (a) Linear regime (b) Saturation regime Table 5.3: Subthreshold swing for various κ p

Conclusion

After evaluating the performance of some elementary circuits with negative capacitance devices, we undertook a study of future technology nodes. We have observed using TCAD simulations that the NC effect can be used to reduce the scale of devices in the next generations (technology up to 5 nm). The subthreshold swing is reduced due to the voltage gain, while the DIBL reduction is due to another phenomenon of barrier increase due to the inclusion of negative capacitance in the gate stack that compensates for the decrease in barrier due to the drain electric field.

Phase Field Modeling of NCFETs In this chapter, we mainly analyzed the effects of interdomain coupling of ferroelectrics on electronic device performance. We analyzed the effect of coupling factor on NC effect of a series resistance ferroelectric capacitor circuit and observed that decreasing coupling factor leads to decrease in negative capacitance due to lower domain wall velocity. We continued this study of the effect of coupling coefficient to device analysis, where we developed a TCAD-based model for simulating NCFETs in various configurations such as with interlayer metal and without interlayer metal with different coupling coefficients.

Future work

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