Modeling, Control and Implementation of DC-DC Converters for Variable Frequency Operation

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Special Issue on International Journal on Advanced Electrical and Computer Engineering (IJAECE) Vol-3, Issue-1 ISSN(Online): 2349-9338, ISSN(Print): 2349-932X

For ONE-DAY National Conference On Restructuring in Indian Power Sector & Smart Grid‖

School of Electrical Engineering, KALINGA INSTITUTE OF INDUSTRIAL TECHNOLOGY, 7th April, 2016 91

Modeling, Control and Implementation of DC-DC Converters for Variable Frequency Operation

1Shailaja Rout, ²Pradosh Ranjan Parida, ³Chinmoy Kumar Panigrahi, ⁴M.Basu,

1,3KIIT University

2Jadavpur University

4Power Engineering Department, Jadavpur University

Abstract : In this work we propose a novel approach in modelling and controller design of the synchronous dc-dc step down converters. Power electronic converters are mainly periodic variable systems due to their variable switched systems. The generalized or enhanced state space averaging is a better approach than state space averaging as it defines them by a unified set of differential equations, capable of representing circuit waveforms. This model is then used to design a PID controller which will help us in understanding the converter dynamics.

Keywords : DC-DC converters, state space averaging(SSA), enhanced state space averaging(ESSA), digital control, variable switching frequency operation, PID controller, Digital Pulse Width Modulation(DPWM)

I. INTRODUCTION

Today, dc-dc conversion is a mature and well- established technology used in a large variety of demanding applications. Yet the control problems associated with such converters still pose theoretical and practical problems. The switching instances can be controlled by reducing loads as well as by controlling the on-time and off-time. The averaging methods are convenient for designing controllers to be applied to switched converters. State Space Averaging has been demonstrated as an effective method for analysis and control design in PWM switching converters. But this method has got limitations with circuits that do not satisfy "small ripple" and "linear ripple" conditions.

Because of these conditions the State Space Averaging cannot be applied to a wide range of circuits. Hence, it means this approach is not suitable for modelling converters which have dominant oscillatory behaviour like resonant type converters and large ripple PWM converters. Hence, the generalized form of state space averaging was developed based on a time dependant Fourier series representation. The Generalized State Space Averaging method is a way to model them as time independent systems defined by a unified set of differential equations capable of representing circuit waveforms. The digital multi-loop proportional integral derivative (PID) controller is based on loop shaping of frequency domain transfer functions. Here the on-time and the off-time of the switching period are used as control inputs. In this way constant on-time and constant

off-time as well as variable on-time and variable off- time can be studied.

II. PROBLEM FORMULATION-

Firstly, a small-signal averaged and linearized model will be derived, in which the on-time ˆton and the off- time ˆtoff of the PWM signal driving the power stage of the dc–dc converter appear as additional inputs to the system. Where the synchronous buck converter will function in continuous conduction mode. The state space models will be designed according to enhanced state space modelling technique and the various matrices will be defined. The proposed ESSA model will be applied to the buck converter with and without the ESL where ESL is the equivalent series inductance. The simulation results of the proposed model will be studied.

III. SOLUTION METHODS

Fig:- schematic view of synchronous buck converter For designing the circuit MOSFET is used as switching devices as it is suitable for high frequency applications.

The values of input and output voltages are taken as 12V and 1V respectively. the output inductor and output capacitor values are taken as 320nH and 660 µF. The switching frequency is kept in between 400kHz<= f_sw

<=1.6MHz where the nominal switching frequency is 780kHz. The parasitic R_Land R_C are taken as 1mΩ again R_on=15mΩ and LC = 1nH. The simulation results are shown considering ESL and without considering ESL. Accordingly, for a synchronous buck converter in continuous conduction mode (CCM), during the on-time the high-side switch S1 is conducting and the low-side switch S2 is open. Whereas during the off-time, the high-side switch S1 is open and the low-side switch S2 is conducting. The relationship between duty cycle, on-

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time and off-time and switching period in equilibrium is given by

D = t_on

Ts = t_on ton + toff

D′ = 1 − D

The state space models as considered in this study are defined as

dx (t)

dt = Ax(t) + Bu(t) y(t)= Cx(t) + Du(t) where A = dynamic matrix B = input matrix C = output matrix

D = direct transmission matrix respectively such that a set of matrices (A_i,B_i, C_i, D_i) describing the system for each switch configuration of the dc–dc converter can now be found, such that i = 1for the configuration during the on-time, whereas i = 2during the off-time. For the proposed PID controller due to the

ESL of the output capacitor, in combination with short on-phases and large current magnitudes, a significant spike-like ripple appears in the output voltage, at the transitions between the on-phases and the off-phases.

For that reason, a first-order low-pass filter (LPF) has been integrated at the input stage of the ADC. The implemented control system will have two control inputs, namely the on-time and the off-time of the DPWM signal driving the power switches. The DPWM block, which is common for both presented control structures, combines the on-time ton and the off-times toff of each period, in order to generate the periodic switching function which is then passed to the output stage of the converter. The on-time is updated once per switching period, whereas the off-time is updated at the rate of the ADC. The analog-to-digital converter (ADC) has been designed with a sampling frequency fadc = Nf(sw,nom),where N is the oversampling factor. In order to avoid limit cycle oscillations at the output voltage, the resolution of the DPWM needs to be greater than the one of the ADC.

IV. RESULT

fig :- simulation result of synchronous buck converter without considering ESL.

fig :- simulation result of synchronous buck converter with considering ESL

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Hence we can see in the results due to the presence of parasitic ESL unwanted spikes are present in the output voltage, whereas the output voltage without considering the ESL provides a smooth output voltage. The ESSA equations for the buck converter when switch S₁ was on and switch S₂ was off are

A1 = [

0 0 1

C 0 −RL+ Ron + Rl

L

Rl

−1 L LC

R_l

LC −R_C+ R_l LC

]

B1 = [0 1 L 0 ]T

C1T = [0 Rl −Rl] D1 = 0

Similarly, when the high-side switch(S₁) is open and the low-side switch(S₂) is closed, again the same dynamic system is obtained, but with the input voltage vi disconnected. the matrices are as followed

A₂ = A₁

B₂ = [0 0 0]T

C₂^T = C₁^T D₂ = 0

fig:- schematic diagram of the proposed PID controller

V. CONCLUSION

In this paper, an alternative and novel formulation of the linearized small-signal models for dc–dc converters has been presented. The proposed modelling approach can be further applied to a wide range of dc-dc converters.

The PID based digital control system exploits the additional insight in the dynamics of a converter under variable switching frequency operation.

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