To correctly estimate the power consumption of the entire design, an accurate memory power model is needed. More importantly, using the neural current model for power estimation does not require any transistor-level or gate-level description of the circuits.
Motivation
With this current model, users can obtain the current consumption of the circuits without detailed circuit information, because it can be derived directly from the current model and the high-level power characteristics. Therefore, in this thesis we propose a new power model for complex digital circuits that uses neural networks to learn the power characteristics during simulation.
Goals and contributions
The basic synthesis process of the Design Compiler (Design Vision) is given in Figure 2.7. The Design Compiler is a powerful tool that other products can run within its environment using specific commands. Before starting the power calculation using the Power Compiler, the desired gate-level netlist of the design must first be generated. During power analysis, the power compiler uses note-switching activity to estimate the power consumption of the design.
As mentioned in Section 3, in our first study for neural network architecture, we chose a connection configuration with full feedforward connection. The first parameter to be decided is the input data format, which is referred to as the characteristic value of input samples to the circuit. Power Compiler requires information about the switching activity of the design for power analysis. These tools work on the port-level netlist of the design along with the port-level power library.
Then the reverse annotation file that has the link activity of the design is read.
Thesis organization
Need for low power design
Design flow with and without power
At each of the design levels, there are two important power factors, namely power optimization and power estimation. Power estimation is defined as the process of calculating the power and energy expended with a certain percentage of accuracy and at different stages of the design process.
Relationship between different abstraction levels
Its pre-synthesis simulation capabilities enable design power consumption analysis at RTL. The following is the approach that was used to calculate power using the Power Estimator that is part of the Power Compiler tool.
Basic concepts of power
Static Power
Dynamic Power
- Switching power
- Internal power
Short-Circuit Power
Leakage Power
Overview of power estimation techniques
The most accurate approach for power estimation is to perform simulation at the transistor level because detailed information about the entire design is known. Compared to other approaches, high-level power estimation makes it much more difficult to obtain highly accurate results because too much design detail is already lost.
High level power estimation
This implies that high-level power estimation techniques are essential for designing such a complex design to shorten redesign cycles. High-level power estimation techniques can be roughly divided into two categories: top-down and bottom-up.
Tools Used
Non power tools
- Simulation tool
- Synthesis tool
The tools discussed in this chapter are some of the non-electrical tools involved in the overall design flow. The next chapter covers each power tool in detail, as most of the thesis involves the use of these power tools. A Verilog or VHDL compiler reads the HDL files and performs compilation and architectural optimization of the designs.
Power tools
- Power Compiler
When combined with the Design Compiler tool, Power Compiler provides simultaneous optimization of timing, power and area. Ultimately, Power Compiler is used to calculate power using the port-level netlist produced by the Design Compiler or the power-optimized port netlist produced by Power Compiler itself. During power optimization, Power Compiler uses the annotated switching activity to make design decisions.
Introduction
The forward switching activity file generated by the “rtl2saif” command as part of the Design Compiler is also passed to the simulator. This power estimation method uses Power Compiler with the same RTL back annotation switching activity used to estimate power using Power Estimator, but instead of RTL code it uses a port-level netlist of the design. As shown in the script, first the gate-level netlist of the adder design obtained from Design Compiler is read into the "dc_shell" environment.
Biological neuron vs. artificial neurons
Biological neurons
Artificial neurons
Feed forward neural network
Operations of neural network
24 parameters, including weights and bias factor matrix, will be modified according to the error measurement so that the error can be reduced. In other words, the weights and biases are modified in response to network inputs only as illustrated in Figure 3-4b. While the weights and bias matrices are fixed after the learning phase, the computation of o for a given x performed by the network is the recall phase.
Training algorithms
Levenberg-Marquardt algorithm
One is the RTL code that is simulated using the ModelSim simulator to obtain a switchback SAIF file that contains the switching activity of the design and is used to create the power model for the design using the “create_power_model” command. Some power tools do not understand the SAIF file, so in this case the VCD file is used. The backward SAIF file generated by the simulation contains the resulting switching activity of the elements monitored during the RTL simulation.
The following is the explanation of each of the command lines in the script. The dc_shell” command is used to call the Design Compiler. a) power_preserve_rtl_here_names = true. Once the netlist is read, the top level of the design is created as the current design to work on.
Steepest Descent algorithm
Properties of the neural network
Summary
Introduction
We will not only focus on the new modeling approach, but also look at the neural network parameters required for the basic building block of the algorithm. However, according to the experience of neural network research, there is no easy or general way to determine the optimal solution for the number of neurons to use [17]. Therefore, in this work we start with a small number and add more neurons until the neural network can learn the features with the desired accuracy.
Parameters of neural network
The complexity of this neural power model has no relation to the circuit size and the number of inputs and outputs, so that this power model can be kept very small even for complex circuits.
Introduction
Benchmark circuit description
Only the highest priority channel in the highest priority requesting bus is recognized. One exception is that if two or more interrupts produce requests on the channel being acknowledged, each bus is acknowledged. The output line numbered 421 actually produces the reverse out[3] response of what is shown in the truth table.
Power estimation techniques
Basic design flow
Depending on the tool, either the RTL-level switching activity or the port-level switching activity is used. This tool should give almost the same power compared to the Power compiler, which uses port-level switching activity. Inputs for power calculation are port-level netlist [3], port-level switching [5], parasitic information [6].
Power estimation at register transfer level
Methodology
Then the design is characterized using the backward labeled switching activity and the power is reported using the “report_rtl_power” command. The following Figure 3.6 shows the current required to obtain the gate level switching activity with Back annotation, which will be used later for the power calculation. The toggle file gives the tool information at which points in the plan the toggle occurs.
Creating forward and backward switching activity
- SAIF file and RTL simulation
- SAIF forward annotation file
- Creating backward SAIF file
Power reporting using power estimator
Power estimation using power compiler with RTL switching activity
Methodology
Another method of calculating the power of a design, which is more accurate than the previous Power Compiler method, is to use the gate-level netlist with gate-level switching activity. Method 42 is better than the previous method because it uses the gate-level net list to obtain the design switching activity, but the time required to do this procedure is more than the previous two methods. Performed Power Estimation for various circuits from RTL level to Gate level using various power estimation tools.
Power estimation using power compiler using gate level switching activity
Creating gate level switching activity
The main difference between the RTL back annotation switching activity and the gate-level switching activity is that here the gate level net-list is given as input to the ModelSim simulator together with the testbench and the do-file, which contains the entire switching region definition and the actual execution of the simulation and reporting of the toggle activity. The do file used to capture switching activity follows the same procedure as RTL switching activity such as defining the reading of the forward SAIF file, defining the region for counting switching information, starting and stopping the monitoring switching activity, and finally using the "toggle_report" command to report the activity in a SAIF file format. The next method discussed is using another gate-level Power Estimator that uses almost the same input files except that it takes in the switching activity as VCD format.
RTL power report
Power report using power compiler with RTL switching activity
Gate level power report
Table 6-1 above shows the input samples we used to train our neural network power model. Our neural power model has very low complexity, so this power model can be applied to complex circuits. We can also try to extend our neural power model to estimate the power of sequential circuits, so that this approach can be applied to all kinds of complex circuits.
Input data for power model
Power comparison
The above Table 6-2 shows the power comparison in the unit of nano Watts, between different neural network backpropagation training algorithms and power compiler. It is observed that Levenberg-Marquardt training algorithm gives better performance compared to steepest descent training algorithm. The comparison result shows that a small amount of errors occur when compared to power compiler.
Summary
Conclusion
According to the related study [35], it suggested to determine the number of samples according to Equation 7.1, where P is the number of samples, |W| is the number of weights to be trained and a is the expected accuracy.
Future work
Najm, "A Survey of Power Estimation Techniques in VLSI Circuits", IEEE Transaction on VLSI Systems, vol. Rabaey, "An Integrated CAD Environment for Low-Power Design", IEEE Design and Test of Computers, s. Liu, "A Novel Approach for High-Level Power Modeling of Sequential Circuits Using Recurrent Neural Networks," IEEE International Symp.
