View of REVIEW ON MINIATURIZED DESIGN BRANCH-LINE COUPLER USING CMOS TECHNOLOGY

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Vol.03, Issue 11, November 2018, Available Online: www.ajeee.co.in/index.php/AJEEE

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REVIEW ON MINIATURIZED DESIGN BRANCH-LINE COUPLER USING CMOS TECHNOLOGY

Akanksha Sanodiya¹, Research Scholar,EC

Prof. Anjan Gupta²,

Adina Institute Of Science And Technology, Sagar, MP, India

Abstract— In this review paper, branch-line coupler(BLC) using CMOS technology is presented. By use of meandered thin-film microstrip (TFMS) transmission line, miniaturized BLC can be obtained. To further decreasing of BLC dimension, capacitive loading technique (CLT) is used. These two techniques results in 0.063 mm2 occupied area, which is leading to a suitable structure for low cost and compact MMIC technology. The design procedure has advantage of the multi-level metallization processes offered in CMOS technology. The analysis is based on a full-wave commercial electromagnetic (EM) package, ADS Momentum. The simulation results provide wideband characteristics impedance over 57-64 GHz frequency band, as well as good transmission loss and isolation between ports.

Keywords— Branch line coupler; millimeter wave; V-band applications; CMOS technology;

I. INTRODUCTION

The unlicensed 60 GHz frequency band (57–64 GHz) by providing 7 GHz available bandwidth has achieved great attention for transmission of high data rate greater than 2 Gb/s for several applications such as high-speed radio systems and WPAN applications [1]. For microwave and millimeter-wave frequency bands, different technologies such as monolithic microwave integrated circuit (MMIC) on GaAs, SiGe or Si, and the miniature hybrid microwave integrated circuit (MHMIC) on very thin ceramic substrates have been used for several circuits and components. In [2], miniaturized millimeter-wave amplifier and mixer for MMIC are presented. By using three- dimensional MMIC technology, a compact wilkinson power divider is given in [3]. A new type of combiner/power divider by use of MHMIC technology is presented in [4]. Different branch-line coupler (BLC) with MMIC and MHMIC are given in literature [5]-[7], as well as phase shifter which is presented in [7].

Design an appropriate BLC is a significant issue in radio systems due to their capability of using in balanced amplifiers, mixers, vector modulators and so on [5]-[10]. Due to the use of quarter- wavelength transmission lines, the BLC occupies large chip areas. Therefore, the realization of these BLC demands several techniques to decrease the size of the couplers to increase the level of system integration as well as reduce fabrication cost. In order to design a 60 GHz BLC, Haroun and et al. [8] used EC-CPW technique that occupied 0.102 mm2 areas

for 90nm CMOS technology. In [9], it is shown that by using EC-CPW as well as TFMS, about 0.086 mm2 area is needed for fabrication. As given by Haroun and et al. in [10], about o.438 mm2 areas is desired for coupler design by using LG- CPW technique for 60 GHz applications.

In this paper, a compact and small-size BLC with good performance on impedance matching, transmission loss, and isolation between ports is presented.

The simulation results of S-parameters, phase and amplitude imbalance as well as the occupied area of the proposed BLC have been compared with the simulation results of some recent relevant work at 60 GHz applications [8]-[10].

Moreover, the amplitude and phase imbalance confirm the capability of the proposed BLC for high-speed radio systems and WPAN applications. The simulation results are provided by a full- wave commercial electromagnetic (EM) simulator, Agilent ADS Momentum. In different papers, it is shown that the results of ADS Momentum are in good agreement with the measurement results [9], [10]. Since, the length of the quarter- wavelength transmission line at 60 GHz (about 750 um) as well as the cost of the SiO2 wafer space are significant parameters, two miniaturization methods named as meandered thin-film microstrip (TFMS) transmission line and capacitive loading technique (CLT) are utilized that results in 0.063 mm2 occupied areas. The proposed BLC is designed on a 130 nm CMOS technology for 57-64 GHz applications.

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2 II.MINIATURIZATION TECHNIQUES

Due to the use of quarter-wavelength transmission lines for BLC at microwave and millimeter-wave frequencies, the basic and elementary BLC block occupies large chip areas. So, it is demanded that several miniaturization techniques to decrease the BLC size are used. Several methods to miniaturize the transmission line, microwave circuits and components have been used. Generally, meandering the transmission lines [11], using lumped elements and replacing transmission lines with them used at low frequency which is inefficient at mm-waves

Fig. 1. (a) Basic transmission line, (b) equivalent reduced-length transmission

line with CLT.

Fig. 2. (a) Basic BLC, (b) equivalent compact BLC with CLT.

circuits [12], and using capacitive loading at the ends of transmission line [14] are the most common techniques. In [14] the capacitive loading technique has been introduced at 11, 25 GHz on GaAs substrate. Recently, because of the achieving great attention for transmission of high data rate for high-speed radio systems and WPAN applications at 60 GHz band, several works have used this technique on MMIC technology as well as the proposed BLC at V-band, [8]-[10]. In principle, increasing the line capacitance and inductance per unit length reduces the signal phase velocity (νp) which leads to a reduction of wavelength (λ . Fig.1 (a) shows basic schematic representation of a transmission line section with length of θ and characteristic impedance of Zo. The

equivalent transmission line circuit with reduced-length line is presented at Fig. 1 (b). The electrical length (θ  and the characteristic impedance (Zo1) of the transmission line are considered. Two capacitive loading with values of C is placed at the end of the shortened line. By equating the admittance matrices of the two-port networks of Fig. 1(a) and (b), the impedance of the shortened line and the capacitance of C can be expressed as below [14]:

Zo1= Zo/ sinθ (1) C = (cosθ− cosθ)/(ω Zo sinθ) (2) where ω is the angular frequency of operation. In order to implement the capacitor, lumped elements or open circuit shunt stubs can be used [14].

Moreover to provide the Fig. 1 (b) circuit, first the desire electrical length is chosen (θ ), and then the line Impedance (Zo1) and the value of the capacitor (C) are obtained by using (1) and (2).

Fig. 3. 2-D view of the proposed coupler at the 60 GHz frequency band

by using meandered TFMS and CLT.

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3 Fig. 4. S-parameters of the

miniaturized proposed BLC (a) S12, (b) S11, S22 and S23

III BRANCH-LINE COUPLER DESIGN Fig. 2 (a) shows a basic BLC circuit with λ  longitudinal and transverse branches with characteristic impedance of Zo and Zo/√2, respectively. The electrical lengths of the longitudinal lines (θ^L) and the transverse branches (θT) are calculated from equation (1) with the similar impedance value of both branches which is shown in Fig. 2 (b). This choice would facilitate the coupler fabrication. The relationship between the coupler’s electrical lengths and their impedances ZLand ZT, are given as below:

sin θL/sin θT = √2 ZT/ZL

Equaling Z^L and Z^T leads to θ^L = π/4 and θT = π/6. So, according to equation (1), the impedance of ranches is 70.07 for Fig. 2(b). Also, the total capacitance at each corner of the coupler, Ceq, is calculated from equation (2), which is equal to 102.5 fF at 60 GHz.

Fig. 2 (b) depicts the equivalent circuit of the coupler which has a significant reduction in size. 2-D view of the proposed coupler of Fig. 2(b), which was simulated using an EM simulator, is given in Fig. 3 (Si- substrate not shown for clarity). In Fig.

3, the dimensions value of BLC and the port name are shown. In order to consider both conductive and dielectric loss, the signal lines are implemented on top metal (copper) layer with thickness of 3.35 μm. To enhance the

propagation loss at compact BLC, the first-metal is grounded to omit the silicon loss. Moreover, to implement the capacitive loading, the top metal layer and the ground strips to form metal-SiO2-metal capacitor are used.

The structure is simulated with a full- wave electromagnetic simulator.

IV.RESULTS AND DISCUSSION

The transmission loss and S-parameters of return loss and isolation between two input ports of the proposed compact BLC is presented in Fig 4 (a) and (b), respectively. The transmission loss varies around -4.5 dB with value of -4dB at the center frequency. Moreover, for the desired frequency bands (57-64 GHz), it is shown that the proposed BLC has reflection coefficient of better than -13 dB at the whole band with value of -19dB at center frequency of 60GHz. Also, the isolation between two input ports of port 1 and port 2 is better than -13 dB with value of -21.4 dB at the center frequency.

The phase difference between two output ports when excited by port 1 is presented in Fig. 5. From the figure, it is obvious that the compact BLC provides 90 ô phase difference while the length of the hybrid branches are 30 ô and 45ô.

The amplitude imbalance (|S31|-

|S21|) and phase imbalance (Phase of S31- Phase of S21) of the two output ports are given in Fig. 6. It is shown that the amplitude imbalance is less than 0.5dB for the whole band and is equal to 0.45 dB at the center frequency. Moreover, the phase imbalance is less than 1.5 ^o with the value of 0.5 ^o at the center frequency of 60 GHz. These results show that the proposed compact BLC can provide stable

Fig. 5. Phase differences between two output ports of the miniaturized

proposed BLC.

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4 Fig. 6. The amplitude and phase

imbalance of the miniaturized proposed BLC.

phase difference and similar amplitude values for V-band applications.

In order to show that the proposed miniaturized BLC for V-band applications by using 130 nm CMOS technology is appropriate, the values of return loss of port 1, transmission loss of port 1 toward port 2, isolation between port 1 and port 4, phase imbalance between port 1 and port 2 or port 3, as well as amplitude imbalance of port 1 to port 2 or port 3 are presented in Table Ι and are compared with the simulation results of [8], [9] and [10]. As presented in Table I, the proposed BLC block provides good behavior at the 60 GHz frequency band. Moreover, the proposed BLC occupied an area about 229 μm × 275 μm (0.063 mm²) on a SiO2 substrate which uses approximately 61%

area of Haroun and et. al works at [8], 73% area of Hetaak and et. al works at [9], and 14% area of Haroun and et. al works at [10].

V CONCLUSION

The proposed compact branch-line coupler (BLC) for V-band with 7 GHz unlicensed frequency band at 60 GHz is proposed. The BLC block can be used for transmitting high data rate in the range of Gb/s for several applications such as high-speed radio systems and WPAN applications. The

Table I.performance comparision of 60ghz branch-line couplers with other

references.

Haroun Hetaak Haroun and et al and et al and et al Our

work [8] [9] [10]

Technology 90 nm 90 nm Glass 130 nm

CMOS CMOS Based

IPD CMOS

Techniques EC-CPW EC-CPW

LG-CPW TFMS

& TFMS & CLT

Return Loss Not

~ 18 ~ 30 19

(dB) mention

Transmission

~ 4.8 ~ 5.6 ~ 3.6 4

Loss (dB )

Isolation

~ 16.5 ~ 20 ~ 32 21.7

(dB)

Phase

5o 6o 0.5^o 0.5^o

imbalance

(degree)

Amplitude

0.7 0.84 0.1 0.5

Imbalance

(dB)

0.086

mm² 0.438

mm² 0.063

mm² The occupied 2 (194×414 (607×722 (229×275

area 0.102

mm μm²) μm²) μm²)

proposed BLC is designed by two miniaturization techniques, meandered thin-film microstrip (TFMS) transmission lines and capacitive loading technique (CLT). The structure is considered for 130 nm CMOS layout.

The signal lines are implemented on top metal layer with thickness of 3.35 μm and for enhancement in the propagation loss at compact BLC, the first-metal is grounded to omit the silicon loss. Moreover, to implement the capacitive loading, the top metal layer and the ground strips to form metal-SiO2- metal capacitor are used. Through the simulation results, it is shown that the proposed BLC block has good return loss, transmission loss, and isolation at the desired frequency band. Also, good amplitude and phase imbalance results of less than 0.45 dB and 0.5degree are provided for the center frequency of 60 GHz, respectively. It is obvious that the

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5 proposed compact BLC is suitable for wireless applications with high data rate and can be easily used in MMIC technology

ACKNOWLEDGMENT

Special thanks to Dr. Rashid Mirzavand at the Institute of Communications Technology and Applied Electromagnetics, Amirkabir University of Technology, Iran, for his useful technical discussions.

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