STUDY OF IMPLEMENTATION OF IMAGE PROCESSING ALGORITHMS ON FPGA
1Deepshikha Soni
1Research Scholar, Dept of Computer Science Engineering, SVN University, Sagar (M.P.)
2Abhishek Tiwari
2Assistant Professor, Dept of Electronics & Communication Engineering, SVN University, Sagar (M.P.)
Abstract:- In This work the methodology enables algorithm developers to iteratively optimize their algorithms while maintaining the level of image integrity required by their application.
Furthermore, it does not require algorithm developers to change their current development process. Rather, the design for implementation methodology is best suited for optimizing a functionally correct algorithm, thus appending to an algorithm developer’s design process of choice.
1. INTRODUCTION
Most often the same individual or group of individuals does not perform both: the design of the high-level model of an algorithm and its implementation.
Algorithm development typically focuses on achieving functional correctness, which comes at the expense of high computational resources. The goal of implementation, on the other hand, is to achieve maximum efficiency.
This means minimal
computational resources, low power, and high execution speed. When algorithms are tailored for efficiency, precision is often sacrificed, creating a dichotomy. The lack of cross-disciplinary expertise may result in valuable optimization opportunities to be missed. During the implementation phase of multi-step image processing algorithms, hardware/software engineers may be reluctant to modify the high-level model of the algorithm to improve efficiency, due to their limited imaging science background.
For these reasons, this work argues that the selection of implementation-efficient operations and optimal number representations, among other algorithm optimizations, should be performed during the high-level modeling of the algorithm. Image processing algorithms are typically developed using a high-level modeling software suite such as MATLAB, Mathcad, or MAPLE.
However, these tools don’t lend well to creating code that can be considered implementation-efficient or
“friendly.” An algorithm whose operations can be mapped directly to a Hardware Description Language (HDL)
and/or in some cases C-code is considered implementation-friendly. In an effort to bridge the gap between disciplines, much work has been done to facilitate algorithm- hardware co-design, as will be discussed in the next chapter.
Algorithms developed in the aforementioned high-level programming languages often use intrinsic function calls that buffer the algorithm developer from the detailed calculations, but result in dead-ends for hardware/software designers attempting to identify fundamental operations. Direct translations of these high-level models into implementations result in overly complex and generally inefficient designs.
By taking advantage of the optimization opportunities present during the development process of the algorithm, as well as applying proper techniques for efficient hardware realization, a maximally efficient implementation can be reached.
Once an image processing algorithm has been passed from the algorithm development phase to the hardware implementation phase, a number of techniques exist for enabling hardware/software engineers to achieve optimal implementations in terms of speed, area, and power consumption [1].
The sequential portions of an algorithm can be pipelined to increase throughput, while other portions that are fundamentally concurrent can be computed in parallel. Other methods such as selective reset strategies and resource sharing can reduce overall resource utilization and congestion.
Figure 1: Block diagram of GSEG algorithm, Reproduced from [4].
1.1 Design for Implementation
Figure 2: The Design for Implementation Iterative Flow.
2. RESULTS AND DISCUSSIONS
The following results represent different image quality metrics for each stage of the algorithm.
Two images were selected from the database, one of which was of two deer (321 pixels by 481 pixels) and another of which was two officers in front of a clock tower (481 pixels by 321 pixels). The test points compare original algorithm results generated in MATLAB with the modified algorithm results generated from implementation within the FPGA.
Figure 3: Two-dimensional correlation coefficients for all modified stages of the GSEG algorithm. The right-hand side shows an enhanced view of the range from 0.99 to 1.00.
Figure 4: (LEFT): The GSEG result in the CIE L*a*b* color space.
Figure 5: (RIGHT): The MCF result in the CIE L*a*b* color space.
Figure 6: (LEFT): The Edge Map generated by the GSEG algorithm in MATLAB.
Figure 7: (RIGHT): The Edge Map generated from successive modules in the MCF.
Figure 8: (LEFT): The GSEG result in the CIE L*a*b* color space.
Figure 9: (RIGHT): The MCF result in the CIE L*a*b* color space.
Figure 10: (LEFT): The Edge Map generated by the GSEG algorithm in MATLAB.
Figure 11: (RIGHT): The Edge Map generated from successive modules in the MCF.
2.1 Logic Utilization, Power Consumption, and Execution Time Table 1: Power Consumption Estimates.
3. CONCLUSION
In this work, a methodology of designing algorithms for efficient implementation is presented and evaluated. A design flow and a list of guidelines are proposed which, when applied, result in more efficient physical implementations. The color space conversion and vector gradient portions of an image segmentation algorithm are used as test vehicles to evaluate the proposed design for implementation methodology.
Applying this methodology in a step-by- step example shows that a number of steps in the calculations can be simplified, approximated, or in some cases removed completely without drastically affecting overall image quality.
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