Transient Simulation Result

IV. Simulation and Analysis 14

4.5 Transient Simulation Result

Fig. 4.10 is the result of transient simulation comparing PT-STI and PD-STI. The load capacitance is 0.1 pF and doping profiles of pn junction are P+doping concentration is 2E20 [#/cm³] and the n- well doping concentration is 8E19 [#/cm³]. Width and length of nmos are 1µm and 1µm. Width and length of pmos are 2 µm and 1 µm. The difference in width between nmos and pmos is due to the difference in mobility between electrons and holes. Width and length of diode are 0.35µm and 0.35 µm. This transient simulation is carried out with operating frequency of 5MHz. We can see when the input voltage is halfV_DD, PD-STI converges more stably to halfV_DD. In addition, the overall transition speed of PD-STI is faster than PT-STI. In particular, it should be noted that when the output voltage goes from state ’0’ to state ’2’, PD-STI is 4.4 ns faster compared to PT-STI. This results are indicating that PD-STI is more suitable for binary-ternary hybrid operation.

I compared PT-STI and PD-STI as Power Delay Product, which is an indicator of the energy efficiency of logic circuits. The device size and doping profile are the same as in the previous slide. These were simulated at load capacitance is 0.1 pF and operating frequency is 10MHz. In the Fig. 4.11, Black line is input voltage, blue line is output voltage of PT-STI and red line is output voltage of PD-STI. As you can see, PD-STI respond faster compared to PT-STI. The results (Table 4.3) show that the average power is almost the same, but the delay has been reduced from 10.8 ns to 6.97 ns. As a result, PD-STI realized a PDP reduction approximately 38% compared to PT-STI.

Figure 4.11:Comparison of transient simulation results with PT-STI and PD-STI at 10MHz.

STI Average Power (µW) Worst Delay (ns) Power-Delay Product (fJ)

PT-STI 2.018 10.8 21.79

PD-STI 1.949 6.97 13.58

Table 4.3: Comparison of energy efficiency as PDP of PT-STI and PD-STI.

Finally, Fig. 4.12 shows the delay improvement result at the minimal gate length of 110-nm technol- ogy node. By applying minimal gate length, the overall delay is reduced due to the increase of device current. The worst delay of minimal gate length case is 2.5 ns and the worst delay of 1µm gate length case is 6.97 ns. we can notice that the worst delay is greatly reduced by device gate length scaling. Table 4.4 shows that PDP of the minimal gate length case improves approximately three times compared to 1µm gate length at 10MHz.

Figure 4.12: Comparison of transient simulation results with 1µm gate length and minimal gate length at 10MHz.

W / L Average Power (µW) Worst Delay (ns) Power-Delay Product (fJ)

1µm / 1µm 1.949 6.97 13.58

1µm / L

_MIN

1.76 2.5 4.4

Table 4.4:Comparison of energy efficiency as PDP of 1µm gate length and minimal gate length.

Chapter V

Further Works

Demonstration of PD-STI operation

Tape-out was carried out doping profile split and area split of pn junction with 1µm gate length and minimal gate length of MOSFET. The top view of PD-STI split is shown in Fig. 5.1 and composed of three sections; PT-STI for reference, PD-STI with normal pn diode, and PD-STI with additionally doped pn diode. After the fabout of DB-Hitek 110-nm CMOS foundry fabrication expected between February and March, PD-STI will be demonstrated by measuring characteristics.

Figure 5.1:DB-Hitek 110-nm CMOS foundry fabrication top view of PD-STI split.

3D stacked design by fabricating PN junction under(or upper) the CMOS

Due to the limits of the device scaling and economic feasibility, 3D stacked IC such as heteroge- neous integration and monolithic 3D (M3D) integration are being extensively studied [17], [18] for a breakthrough to achieve ”More Moore and More Than Moore”. In accordance with this flow, if the pn junction capable of low-temperature fabrication can be fabricated in 3D upper or under the CMOS, as shown in Fig. 5.2, the top view area is reduced. In addition, the interconnect wire length can be greatly reduced, thereby realizing latency improvement and power reduction [19].

Figure 5.2:Top view area reduction by forming pn junction under or upper CMOS.

Chapter VI

Conclusion

In order to overcome the power density limit faced by binary-based devices, ternary-based logic system would be a novel technology for the most effective and fundamental solution.

In this thesis, I have proposed a novel standard ternary inverter (STI) circuit design (PD-STI) using 4 transistors and 2 pn junctions based on Si-CMOS technology for compact STI design. Replacing pass transistors (4 terminal device) of PT-STI with pass pn junctions (2 terminal device), reduced the number of interconnects and required V_{T H}. To solve transient operation issue of failing to respond to the input frequency, heavily doped pn junction was exploited, allowing STI to operate at 10MHz.

From the theoretical validation and numerical simulation, PD-STI operation have been verified. I had characterized the remarkable PDP enhancement compared to previous research.

Finally, the proposed STI design; PD-STI can simplify existing STI design using 6 transistors. Fur- thermore, compact design is possible through a monolithic 3D integration or heterogeneous integration.

The proposed PD-STI provides a promising route for future electronic device and circuit in multi- valued logic to break through peta-level information density in the era of the 4^thIndustrial Revolution.

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Acknowledgement

First of all, I would like to appreciate committee professors,

Prof.

Kyung Rok Kim,

Prof.

Seong-Jin Kim, and

Prof.

Myungsoo Kim for giving meaningful interactions and advice on my master’s degree thesis defense.

I would like to express my deep and sincere gratitude to my advisor,

Prof.

Kyung Rok Kim. My professor have emphasized self-motivation that comes from own curiosity to step forward to the next level. My professor’s infinite stimulation that arouses curiosity and motivation pushed me to sharpen my thinking and brought my work to a higher level. Thanks to a great professor, my master’s degree course was very meaningful and it led me to the next level of Ph.D. course.

I would like to express my gratitude to the all members of

NEEDs Lab

,

Dr.

Min Woo Ryu, Sang Hyo Ahn, Youngeun Choi, Woo-Seok Kim, Yu Bin Song, Myoung Kim, Seung Woo Hong, and Minjae Kim who give warm advice and brilliant questions. Thanks to them, I was not lonely, I was able to overcome difficulties about private matters and break through when I was blocked from research. In particular, I would like to thank

Dr.

Min Woo Ryu for giving me a lot of research and life advice in a comfortable place, and I would like to thank Sang Hyo Ahn for being a strong supporter with reliable and warming care. Although two years was a short time, I could definitely tell they have been and always will be really good people.

Also, thank you for excellent alumni,

Dr.

Jong Yul Park,

Dr.

Sung Ho Kim,

Dr.

E-San Jang, and

Dr.

Jae Won Jeong for being a good example of a passionate researcher. I learned where and how to go on a path of a researcher by looking at their footsteps.

Last, but not least, I would like to express my special thanks to my parents, Woo Seong Jun and Nam Young Jung for giving birth to me in the first place and supporting me spiritually throughout my life with their endless love and encouragement, and I also thank you to my sister Soo Jin Jun and my twin Hye Bin Jun for their unconditional support.

With this in mind I will dedicate myself harder in the future.

Dec. 24. 2021.

Jae Hyeon Jun

Curriculum Vitae

Jae Hyeon Jun

Email : jhyeon97@unist.ac.kr Mobile :+82-10-7257-5770 Birthday : November 20th, 1997

Address : Engineering Building 106-602,

50 UNIST-gil, Ulsan 44919, Republic of Korea

Education and Experiences

Mar. 2020 ∼ Feb. 2022 M.S.in Department of Electrical Engineering, UNIST, Korea

Advisor: Prof. Kyung Rok Kim (krkim@unist.ac.kr, http://NEEDs.org) Mar. 2016 ∼ Feb. 2020 B.S.in Electrical and Computer Engineering, Ajou University, Korea Mar. 2013 ∼ Feb. 2016 Gyeongsan High School, Gyeongsan City, Korea

Domestic Conference Presentaions

• 2022 KCS:

Jae Hyeon Jun, Young Eun Choi, Woo-Seok Kim, Seung Woo Hong, Myoung Kim, Su Hyeon Jo, and Kyung Rok Kim,

“Design of Pass Diode-Based Low-Power Ternary Inverter Circuit”, The 29th Korea Conference on Semiconductors, Jan.24-26, 2022

• 2021 KCS:Poster presentation

Jae Hyeon Jun, Jae Won Jeong, Young Eun Choi, Woo-Seok Kim and Kyung Rok Kim,

“Analysis and Characterization of Pass Transistor-Based Ternary Inverter for Optimized Low- Power Design ”,

The 28th Korea Conference on Semiconductors, Feb.25-29, 2021

Patents

• [KR Applied, 10-2021-0084150] 3진수

논리회로

(CNT

기반)

Inventors: Kyung Rok Kim, Jae Won Jeong, Young Eun Choi,Jae Hyeon Jun