However, the power density limit is faced to process large amounts of information, and new approaches for a breakthrough are required. Multi-valued logic (MVL) is one of the new approaches to overcome the power density limit, while reducing the complexity of the circuit by moving from a binary to a ternary. The MVL circuit has fewer logic gates and connections compared to the binary logic for the same function by calculating multiple values in a logic gate, so it is more efficient in power consumption, interconnection complexity, and the gate counts.
In this thesis I propose a new design of a standard ternary inverter (STI) circuit with a minimum number of transistors, which consists of 4 transistors and 2 pn junctions. By utilizing pn junction, the proposed STI reduces power consumption when the output voltage is VDD/2. In addition, the number of interconnections and area is reduced by replacing transistors (4-terminal device) with pn-junctions (2-terminal device).
The STI circuit was simulated with the 110nm technology node model library using HSPICE and Virtuoso. From the simulation results, the proposed STI shows a significant reduction in power delay product (PDP); 38% compared to the state-of-the-art STI of existing STI models.
![Figure 4.8: Analytically calculated P-N junction characteristics when the P+ region doping concentration is fixed to 2E20 [#/cm 3 ] and the N- region doping concentration is increased from 1E18 [#/cm 3 ] to 8E19 [#/cm 3 ]](https://thumb-ap.123doks.com/thumbv2/123dokinfo/10486732.0/10.892.104.788.127.357/figure-analytically-calculated-junction-characteristics-concentration-concentration-increased.webp)
Issue : The Power Density Limit
Motivation : Multi-Valued Logic
PD-STI consists of a positive ternary inverter (PTI) and a negative ternary inverter (NTI), as shown in figure. DT-STI and PT-STI require three VT H types, as shown in Table 3.1, while PD-STI requires only two VT H types. The result shows that the voltage transfer curve of PD-STI is almost the same as that of PT-STI, and the length of the half-VDD state is longer than that of DT-STI.
From this result, it can be seen that the PD-STI design, which replaces the pass transistor PT-STI with a pass diode, has no problem in triple operation and also reduces the types of VT H. Finally, the PD-STI is compared with the PT-STI, which is the state-of-the-art STI . The VT H of the transition transistor in the PT-STI was designed by [14] as a highVT HMOSFET. However, the PD-STI junction region consists of identical pn junctions, so the output resistance is the same.
4.2(a), it can be seen that the halfVDD state of PT-STI is slightly floating due to the difference in resistance between nmos and pmos of the transition region, while the halfVDD state of PD-STI converges stably with the same output resistance of the transition region. If the input voltage of PT-STI and PD-STI is half of VDD, the low VT H nmos and low VT H pmos connected to GND and VDD are turned on and current flows from VDD to GND along one current path. Therefore, VDD consumes the same current in PT-STI and PD-STI regardless of the amount of current in the transition region because the devices connected to GND and VDD are the same.
4.2(b), the power consumption of PT-STI and PD-STI is almost identical when the input voltage is halfVDD, because low VT H nmos and low VT H pmos connected to GND and VDD are the same in both cases PT-STI and PD-STI . We can see that when the input voltage is halfVDD, PD-STI converges to halfVDD more stably. In particular, it should be noted that when the output voltage goes from state '0' to state '2', PD-STI is 4.4 ns faster compared to PT-STI.
These results indicate that PD-STI is more suitable for binary-ternary hybrid operation. I compared PT-STI and PD-STI as a Power Delay Product, which is an indicator of the energy efficiency of logic circuits. 4.11, black line is input voltage, blue line is output voltage of PT-STI and red line is output voltage of PD-STI.
Related Works 4
Challenge of Previous Ternary Logic Circuit
PT-STI is composed of three VT H types of FET which are low VT H (empty box), medium VT H (shaded box) and high VT H (black filled box). The approach of PT-STI is to turn off the transistor at halfVDD so as to generate halfVDD state with a low current. 2.3(b), the power consumption at the half-VDD is significantly reduced from 265 nW DT-STI to about 1 nW PT-STI.
I propose an STI design that replaces the pass transistor in the PT-STI with a pn junction (fig. 3.1). DT-STI and PT-STI have been simulated Synopsys HSPICE with a 32nm MOSFET-like CNTFET library [10], [11]. The pass region of PT-STI is composed of pmos and nmos, so the output resistance is different.
In the case of heavily doped pn junction, the BTBT current is dominant over the reverse bias current. After the DB-Hitek 110-nm CMOS foundry fabout is expected between February and March, the PD-STI will be demonstrated by measuring characteristics. The proposed PD-STI provides a promising path for the future electronic device and circuit in multi-valued logic to break the peta-level information density in the era of the 4th Industrial Revolution.
Proposal of Standard Ternary Inverter Design 7
STI Operation Principle
3.2(b), the PTI voltage characteristic is a yellow line with longVDD output, and NTI is a blue line with long GND output. In short, it can be said that tri-states are created by these two voltage transfer curves. 3.4(a)), when the input is VDD/2, lowVT Hnmos and lowVT Hpmos turn on and transfer GND and VDD respectively to each pn junction.
And then, due to the opposite bias of both p-n junctions, VDD/2 is transferred to the output node. And then, due to the forward bias of PN2, GND is transferred to the output node.
STI Charateristics
And then power delay product (PDP) is calculated with a product of the average power consumption and the worst delay. To solve transient simulation problem, it should increase the reverse bias current and the bias voltage of near 0 V current of the diode. If heavily doped pn junction is exploited, the reverse bias current and the forward bias current of near 0 V diode increase, so this can be a way to solve the transient simulation problem.
To analyze whether the current of a heavily doped pn junction affects the transient operation of STI, transient simulation is performed with the analytically calculated pn junction model in the previous section. We can see state '0', '1' and '2' converge stably and rapidly as the pn-junction doping concentration increases as shown in Fig. The load capacitance is 0.1 pF and doping profiles of pn junction is P+doping concentration is 2E20 [#/cm3] and the n-well doping concentration is 8E19 [#/cm3].
The strip was made by dividing the doping profile and dividing the pn junction region with a gate length of 1 µm and a minimum MOSFET gate length.
Simulation and Analysis 14
DC Simulation Result
Transient Simulation Issue
Solution of Transient Simulation Issue
There is a successful ternary device study known as ternary-CMOS (T-CMOS) [16] using BTBT current caused by heavily doped pn junction. The doping concentration and junction thickness of the pn junction are measured using Technology Computer-Aided Design (TCAD). In case of heavily doped pn junction, BTBT current is dominant in reverse bias region.
Equation (4.2) depicts BTBT current density which is a physical origin of gate induced drain leakage (GIDL) on high electric field area of drain edge. So, using analytical equation of BTBT current, I can build a model of heavily doped pn junction current characteristic. The total diode current is expressed as the sum of the diode current and the BTBT current from the fitted analytical equation.
4.8, from 5E18, we can see a little BTBT current in reverse bias and from 5E19, we can see a large BTBT current in forward bias. As expected, the reverse bias current and forward bias current from near 0 V increase as the doping concentration increases.
Transient Simulation Result
The difference in width between NMOS and PMOS is caused by the difference in mobility between electrons and holes. Applying a minimum gate length reduces the overall delay due to the increase in device current. The worst delay at minimum gate length is 2.5 ns and the worst delay at 1 µm gate length is 6.97 ns.
Due to the limits of device scaling and economic feasibility, 3D stacked IC, such as heterogeneous integration and monolithic 3D (M3D) integration, are being studied extensively for a breakthrough to achieve "More Moore and More Than Moore". To solve the transient operation problem of failing to respond to the input frequency, heavily doped pn junctions were utilized, allowing the STI to operate at 10MHz. A survey and guide on modern aspects of multivalued logic and its application to microelectronic circuits.IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
16] Jae Won Jeong, Young-Eun Choi, Woo-Seok Kim, Jee-Ho Park, Sunmean Kim, Sunhae Shin, Kyuho Lee, Jiwon Chang, Seong-Jin Kim and Kyung Rok Kim. My professor has emphasized self-motivation that comes from one's own curiosity to step to the next level. Thanks to a great professor, my master's degree was very meaningful and led me to the next level of Ph.D.
Jae Hyeon Jun, Young Eun Choi, Woo-Seok Kim, Seung Woo Hong, Myoung Kim, Su Hyeon Jo en Kyung Rok Kim. Design of Pass Diode-Based Lae-Power Ternary Inverter Circuit”, Die 29ste Korea Konferensie oor Halfgeleiers, Jan. Jae Hyeon Jun, Jae Won Jeong, Young Eun Choi, Woo-Seok Kim en Kyung Rok Kim,.
