Computer Architecture
Exception Handling and Advanced
Pipelining
Computer Architecture & Network Lab 2
Datapath with Controls to Handle Exceptions
Exception Handling Example
overflow exception
Computer Architecture & Network Lab 4
Exception Handling Example
start of exception handling routine
Advanced Pipelining
Superpipelining
Superscalar
Dynamic Pipeline Scheduling
Computer Architecture & Network Lab 6
Superpipelining
IF-1 IF-1 ID EX-1 EX-2 MEM WB
IF-1 IF-1 ID EX-1 EX-2 MEM WB
IF-1 IF-1 ID EX-1 EX-2 MEM WB IF-1 IF-1 ID EX-1 EX-2 MEM WB
IF-1 IF-1 ID EX-1 EX-2 MEM WB
Superscalar
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
ALU or Branch Load or Store
ALU or Branch Load or Store
ALU or Branch Load or Store
ALU or Branch Load or Store
Computer Architecture & Network Lab 8
Superscalar Pipeline
Simple Superscalar Code Scheduling
Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result
addi $s1, $s1, -4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0
Computer Architecture & Network Lab 10
Scheduled Code
ALU or Branch Load or Store Cycle
Loop: lw $t0, 0($s1) 1
addi $s1, $s1, -4 2
addu $t0, $t0, $s2 3
bne $s1, $zero, Loop sw $t0, 4($s1) 4
Loop Unrolling
ALU or Branch Load or Store Cycle Loop: addi $s1, $s1, -16 lw $t0, 0($s1) 1
lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw $t0, 16($s1) 5 addu $t3, $t3, $s2 sw $t1, 12($s1) 6 sw $t2, 8($s1) 7 bne $s1, $zero, Loop sw $t3, 4($s1) 8
Computer Architecture & Network Lab 12
Dynamic Pipeline Scheduling
• Example: Power PC 604, Pentium Pro, Alpha 21264, MIPS R10000
Dynamic Pipeline Scheduling
Overcome key performance limitations of in-order pipeline instruction execution
Structural hazard
− Replicate pipelines
Data hazard
− Execute instructions out of program order
− Rename registers as needed
Control hazard
− Execute instructions speculatively across branches
Computer Architecture & Network Lab 14
Dynamic Branch Prediction
predict taken predict not-taken
taken not-taken
taken not-taken
One-bit prediction scheme
Problem : Loop case
Dynamic Branch Prediction
predict taken
predict not-taken
taken not-taken taken
Two-bit prediction scheme
predict not-taken predict taken
not-taken
not-taken taken
Computer Architecture & Network Lab 16
Summary
Three major handles in pipelined implementation
Structural hazard
Data hazard
Control hazard
Advanced pipelining
Superpipelining (clock cycle time ↓)
Superscalar (CPI ↓, possibly < 1)
Dynamic pipeline scheduling
− Structural hazard: resource replication
− Data Hazard:
out-of-order execution
Register renaming
− Control Hazard: speculative execution
