Design of an ASK RF Transceiver for ETCs with Hybrid ASK Modulator and Ultra Low Power Wake-Up Receiver
Yeon Jun Kim
1, Jae Hyung Jung, Tae Seob Oh, Jae Bin Kim, Jong Wan Jo, and Kang Yoon Lee
aDepartment of Department of Electrical and Computer Engineering, Sungkyunkwan University E-mail : 1 [email protected]
Abstract - This article proposes a transceiver structure of RF with modulation by Amplitude-Shift-Keying (ASK) for ETCs (Electrical Toll Collection system). To meet Korean and Chinese standards, the modulator of TX supply to propose a method of hybrid approach. The Korean model is 1024 kbps, the Chinese OBU is 512 kbps and the road-side-unit (RSU) has a data transfer speed of TX of 256 kbps. The hybrid structure has advantages over the analog type in terms of area, energy consumption, process, voltage, variation of PVT. The China ETC way is working with battery and should reduce the energy consumption. The transceiver of main RF is switched off until the Wake-up receiver (WuR) receives the Wake-up signal of the RSU, for what most of the time that the Wake-up receiver is working is busy, so it is essential to minimize power consumption of the WuRx. In WuRx, the detector involving the envelop detection of the Wakeup signal using the current feature of the MOSFET which operates in the region of the sub- threshold, which allows the operation with ultra-low power.
The digital filters are used to improve the reliability of the alarm signal. In these ways, the Wakeup block's total power consumption is 3.6uA. ETC operates when On-Board-Unit (OBU)'s Road-Side Unit (RSU) at high speed. Therefore, the automatic control of gain of RX is not supported in this work.
In the common RX, there is an automatic controller of gain to avoid saturation of Rx power. But even ETC cannot adjust the gain, for what it takes a performance of the receiver with an extended Rx dynamic range when used as with a steady gain.
To comply with the highest P1dB specification and the wide dynamic range of Rx, the receiver proposes a structure for demodulating the ASK signal with LNA, mixer and Received Signal Strength Indicator (RSSI). The Rx dynamic range is 70dB. The transceiver is implemented in a 1P8M CMOS process of 130 nm, with an active area of 3.5mm × 3.5 mm, including the ESD protection pads.
Keywords—ASK, Hybrid approach method, Wide dynamic range
I. INTRODUCTION
Dedicated short-range communication (DSRC) is short- range wireless communication to provide intelligent transportation system (ITS) services. DSRC is a dedicated
short-range communication between a Road-Side Unit (RSU) and an OBU mounted on the vehicle. International companies in South Korea, the United States, Europe, China and Japan are conducting DSRC standardization. DSRC not only provides automatic toll systems, but also provides various services such as traffic information services, road introduction services and logistics services. The main characteristic of DSRC communication is that data transmission is in a narrow field of communication. The implementation of OBU at a small price can not only reduce the investment cost of building the ITS communications infrastructure, but also enable early services to disseminate.
Therefore, the terminal hardware/software must be designed with a simple structure and reduced ASIC power consumption. ETC requires user authentication and encryption functions, as well as error-free data transmission to ensure proper charging.
The objective of this article is to design the RF transceiver required for the RSU and the OBU of ETC 5.8 GHz band (Korea-China). It is reported that there are several approaches for the 5.8 GHz DSRC transceiver. Each country requires different specifications. Especially in China, OBU uses batteries not mounted on the vehicle. Therefore, low power consumption is an essential consideration for extending battery life. The first major difference is the speed of the TX data. TX ASK modulators usually use analog modulators [1-6]. The analog modulators have limitations in controlling the modulation index and have the disadvantage of causing signal distortion. Reference [6] suggests using an exponential current source for the analog temperature compensation, but consumes more current and layout space.
The analog circuit is very vulnerable to PVT variations and the pulse shaping filter requires a large area. Furthermore, larger area is required to support multiple data streams.
Compared to the analog one, the ASK digital modulator has lower sensitivity than the PVT and smaller circuit area, but there is the problem of counterfeiting the digital clock [7].
Another difference between the two standards is that WRx only exists in Chinese mode. Since ETC in China is running on battery power, the Always-On module plays a key role in power saving modes such as WuRx, the oscillator and power management circuits. In the case of low power consumption, high WuRx sensitivity, WuRx in the main transmitter and receiver modules, battery life is reduced and overall performance is degraded. Many WuRx circuits have been studied in the literature to optimize energy consumption, maximize sensitivity, and improve reliability [8].
a. Corresponding author; [email protected]
Manuscript Received Feb. 22, 2022, Revised Nov. 20, 2022, Accepted Dev. 19, 2022
This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/4.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
II. EXPERIMENTS A. ASK RF Transceiver architecture
Fig. 1 is an upper functional diagram of an RF transceiver for DSRC applications. There is a mode conversion function that supports both Korea and China modes. In China mode, WuRx is still functioning as a module still activated, TRX can only function when it receives the wake-up call. In Korean mode, the WuRX module is disabled and TRX has nothing to do with the wake-up call. The TX module is a hybrid ASK modulator structure based on the power modulator, consisting of a TX, PA and PLL modulator. The RX front block consists of an LNA, a mixer, a polyphase filter (PPF), a filter, an RSSI, an ASK demodulator, there are LDOs that power the circuit, crystal screwdrivers that drives the X-TAL into the circuit, and temperature sensors that compensate the temperature. To support both Korean and Chinese modes, the blocks for changing the setting values are WuRx, TX Modulator, PLL, BPF, and the idea of minimizing the area when changing the mode was proposed.
In China mode, the IF signal uses 10 MHz on the low IF structure. In that case, a special case of the image frequency must be received. Therefore, in order to suppress it, the circuit control would be changed. When PLL changes modes in Korea and China, a frequency adapter is used and fast locking technology is adopted. RFC provides fast control signal values when switching between TX and RX modes.
SPI communication with the modem. There are temperature sensors, which can adjust the circuit's timing according to the temperature. The temperature condition is confirmed by a numerical value in the modem and the circuit delay is controlled by a value stored in the correspondence table.
WuR LDOs
Fractional PLL
TX
Modulator DriverXTAL
RSSI 10bitADC RFC
SPI ASK Demod RSSI
PPF main
Temp sensor 4bit
ADC
PA
Atten LNA
REF_CLK Korea China
RF_DSRC
TX_DATA XOPXONRF_CLK WAKE_OUT WAKE_PD RF_PDLDO_OUTsLDO_IN
RX_DATA
Kor/China TRX_SEL
SPI_read INT_PD
Mixer
REF_CLK Kor/China Kor/China
SPI_read
REF_CLKSPI_read SPI_REG
Fig. 1. Top Diagram for DSRC RF Transceiver B. ASK RF Transceiver architecture
Fig. 2 shows the upper functional diagram of the TX ASK modulator. The TX modulator consists of a pulse shaping controller, an 8-bit DAC, an LPF, a power modulator and a PA.
Fig. 2. TX ASK Modulator Top Diagram C. Wake-up Receiver
Fig. 3 shows the functional pattern of the top of the ultra- low-power wake-up receiver. The wake-up receiver consists of an envelope detector, a gain Stage, comparator, a wake-up receiver controller, ULP BGR, ULP LDO, ULP OSC. The envelope detector detects 5.8 GHz RF signals and generates 14 kHz IF signals. The gain block amplifies the IF signal generated by the envelope detector. The comparator converts the signal generated by the gain stage into a digital signal that the Wakeup receiver controller can recognize. An ultra- low power oscillator operating at 256 kHz.
Fig. 3. Top Diagram for Wake-up Receiver D. Low Noise Amplifier (LNA)
Fig. 4 shows the proposed LNA structure. This study integrates controlled S21 with output capacitors into the LNA. The Cap Bank is controlled by a Class 55F 3-bit hot decoder. The total accordable range is 55F ~ 440F. Thus, the maximum value of LNA band is between 5.5. GHz and 6.1 GHz. The gain control method uses two PMOS connected to the LNA + and - outputs. Using the Ron resistance of PMOS, the charge changes and the gain of the LNA changes. The main structure of the LNA consists of two Common Gate amplifiers with inductive loads. Matching input power (S11) is done internally. For the generated differential signal, the first Common Gate stage provides a 180-degree phase signal, and the second stage reverses the signal again, generating a zero-degree phase shifted signal.
Vout- Vout+
MN1 MN2
MN3 MN4
MN5 MN6 IN
VDD VDD
L1
C3 CT0 CT1
C5
RF
G_FCTRL0 G_FCTRL1 G_FCTRL2
G_FCTRL0
G_FCTRL1
G_FCTRL2
VB1 VB3
VB2 C1
C2 C4 CT2
G_FCTRL3 G_FCTRL5
G_FCTRL3
G_FCTRL4
CT4 CT3 CT0 CT1 CT2 CT3 CT5
LMN
VDD
VDD
G_FCTRL4
CT4
G_FCTRL4
Fig. 4. Top Diagram for LNA
TX_DATA REF_CLK
PA RF_IN
PA_OUT MI<4:0>
Pulse Shaping Controller
DAC8bit LPF Supply
Modulator
VMOD VGA
VGA
PA_VDD 1 nF
PA_VDD PAD
INP INN PCW<7:0>
MODE<1:0>
Envelope Detector
Gain Stage Comparator Wake-up Pattern
IN Wake Up
Receiver Controller ULP OSC
WAKE_OUT CLK
ULP LDO ULP BGR
E. Double Balanced Active Mixer
Fig.5 shows the structure of the proposed Double- Balanced Active Mixer. The LO noise voltage is converted into currents of different polarities by pairs of double- balanced switches, summed and suppressed, so that it is less sensitive to LO noise. In addition, using the current mixing technique, the auxiliary transistor is activated at the LO swing intersection, allowing most of the current in the switch pair to flow, thereby reducing the polarization current in the switch pair and reducing the flickering noise. In addition, using PMOS and resistors, the charging stage is realized in the form of a CMFB (Common Mode Feedback circuit), which stabilizes the drain voltage of each switch, prevents the common voltage drop caused by the switch and improves linearity. Furthermore, with limiting the margin, the resistance increases, the conversion gain increases, and the noise value is minimized relative to the existing structure.
Fig. 5. Proposed Structure for Double Balanced Active Mixer F. Poly Phase Filter
Fig. 6 shows the proposed polyphase filter structure.
Image rejection is only used in Korean mode, so the mode can be changed according to Chinese/Korean mode. The continuous manual RC filter moves the phase, rotates the I and Q signals by 45 degree and separates the desired signal from the image signal, so the image signal can only be attenuated. While the higher the order, the better the image rejection performance, with increasing path loss and amplitude/phase inconsistency, consists of a second step, after image rejection, which maximizes the additional image rejection of the baseband simulation to receive Korean mode signal.
Fig. 6. Schematic Design of Poly Phase Filter
G. Received Signal Strength Indicator (RSSI)
Fig. 7 shows the recommended RSSI block diagram. By implementing a logarithmic function of the RSSI structure, a linear graph of the signal power intensity can be obtained.
It is mainly used to monitor input signal power. The circuit is constructed to achieve the final RSSI by connecting the amplitude-limiting amplifier and the on-wave rectifier in series into one unit. Increasing the number of single-cell batteries in series reduces the gain requirement for a single limited current consumption but increases the pole. This results in increased power consumption along with reduced bandwidth. Therefore, considering this issue, the trade-off will take the form of an eight-stage cascade. The cascaded configuration also minimizes the RSSI output error by re- applying the VCM after each step of the input DC offset because DC offset from the front stage is constantly added to the desired signal. Given this straightening step, the bandwidth of the limited amplitude amplifier should allow for a margin.
Fig. 7. Proposed Received Signal Strength Indicator Block Diagram
H. Phase Locked Loop (PLL)
Fig. 8 shows a block diagram of the proposed PLL structure. It consists of PFD, CP, VCO, /8TSPC divider, SDM's decimal N divider, and an external third-order loop filter. The proposed simulated phase-locked ring is used as a fraction-N frequency synthesizer with the following frequency output: The counter-N divider parameters (PC, SC, MC) are randomly changed by the delta-Sigma modulator to reduce fractional spurt. It also enables fast locking through Automatic Frequency Correction (AFC) of the digital synthesis module.
Fig. 8. Block Diagram of analog PLL
IOUTP IOUTN QOUTP QOUTN
VB2
VB2 ILOP ILON
VB2
VB2 QLOP QLON
VB1 VB1
INP INN
Active Load
Current Bleeding
I+
I- Q+
Q-
I+
I- Q+
Q-
Input
Limit Amp
Full-wave
Revtifier LPF
OUTPUT
PFD
~
Fractional-N
3rd_LFEXT
QVCO
CP
DSM
TSPC/8 32.768 MHz
BUF 5.79 ~ 5.88 GHz
Coarse Counter
VCO Frequency/2 PC<4:0> SC<2:0>
MC<21:0>
To compensate for temperature-related variations in QVCO, a compensating MOS varactor is added. This technology compensates for temperature-related capacitance values in LC tanks by receiving output from PTAT-based temperature sensors. The tail inductance reduces phase noise.
Fig. 9. Schematic of QVCO
III. RESULTS AND DISCUSSIONS
Fig. 10 shows the recommended PCB for the DSRC ASK RF transceiver. It consists of DSRC ASK radio frequency transmission IC, 32.768 MHz crystal, antenna, and TRX common matching network. At 5.8GHz frequency, the distance between the antenna and the chip was shortened to minimize RF port loss, and the number of external devices was reduced, while conventional TRX matching was used.
Fig. 10. Measurement board of ASK RF Transceiver
Fig. 11. Layout of the ASK RF transceiver
Fig. 12 shows the measurements in the TX section. RF matching is achieved by S parameters and Smith's circle graphs. If the PA output is set to 6.1 dBm, the reference spurt is 16.384 MHz-43.3 dBc. Finally, the ASK transpose waveform of TX. This is the waveform measured in the time domain where DATA_ is received and TX modulated.
Sending IN signals through the modem.
Fig. 12. Measurement result of TX
Fig. 13 shows the measurement results for the RX and BBA components. In RX measurement, use a network parser to measure the S parameters and use the same values to measure the TX status and match the network. The total noise figure for RX is 8.28 dB and the LNA gain is 15.3 dB.
After applying the AM modulated radio frequency signal to the antenna, the oscilloscope confirmed that it outputs a 4- trigger signal through the BBA test port.
Fig. 13. Measurement result of RX and BBA
Fig. 14 shows the measurements of the Wakeup receiver section. The 14KHz IF signal is fed into the Wakeup receiver through the antenna of the 5.8GHz carrier signal. Wakeup signal is applied periodically. The input number of the OOK signal can be controlled from 1 to 18. Wakeup signal at 5.8GHz and OOK signal at 14kHz are generated at ED_. The OUT signal is processed by digital circuits and the Wakeup signal is generated by the Oscilloscope.
Cap Bank L VDD
Compensation Varactor
I+ I-
Cap Bank L VDD
Compensation Varactor
Q+ Q-
I+ I- Q+ Q-
SensorTemp
Fig. 14. Measurement result of Wake-up Receiver
TABLE I. Performance Summary
This Work [1] [2] [3]
Process 0.13um
CMOS 0.13um
CMOS 0.13um
CMOS 0.13um
CMOS
Mode Korea
China China Korea/Japan China
RF frequency
(GHz) 5.79 ~ 5.84 5.77 ~ 5.84 5.815 ~ 5.845 5.815 ~ 5.845
NF 7.25 dB - 8 dB -
TX power -10 dBm ~
10dBm 5 dBm 11.7 dBm -27 dBm
~ 7 dBm RX data rate 1024 kbps,
256 kbps, 128 kpbs
512 kbps,
256 kbps 1024 kbps 512 kbps sensitivity RX
(dBm) -88 -85 -80 -86
Current
consumption 70mA (TX)
40mA (RX) 46mA(TX)
19mA(RX) 150mA(TX)
52mA(RX) 58
mA(TX) Modulation
index 0.1 ~ 1 0.45~0.95 0.55 ~ 0.96 -
input
P1dB(dBm) -10 - -41 -
Wakeup sensitivity
(dBm) -60 -44 - -35
Wakeup
Current(uA) 3.6 uA 8 uA - 15 uA
IV. CONCLUSION
In this paper, an amplitude-shift keying (ASK) radio frequency transceiver structure for the ETC is proposed. To meet Korean and Chinese standards, the TX power modulator proposed a hybrid method. The Korean model is 1024 kbps, the Chinese OBU is 512 kbps, and the Road Side Unit (RSU) is 256 kbps in TX data transfer speed. Hybrid architectures have more advantages in terms of area, power consumption, and PVT variation. China mode ETC is battery powered and power consumption should be reduced. Since the main radio frequency transceiver is switched off until the wake-up receiver (WuRx) receives a wake-up signal from the RSU, the wake-up receiver takes up most of the operation time of the wake-up receiver, minimizing current consumption of the wake-up receiver. In the wake-up receiver, the envelope detector detects the envelope of the wake-up signal using the current characteristic curve of the MOSFET operating in the subthreshold region, so it can operate at ultra-low power consumption. Digital filters are used to improve reliability of wake signals. The total current consumption in the wake-up module is 3.6uA.
ETC communicates when the OBU is high-speed through the RSU. Therefore, RX automatic gain control is not possible. An automatic gain controller is required for normal receivers to avoid saturation of Rx power. However, the ETC
cannot adjust the gain and therefore requires a wide range of receiver performance when setting the fixed gain. To satisfy the high P1dB specification and wide Rx dynamic range, the receiver proposes a structure to demodulate ASK signals with LNA, mixer and Receiving Signal Strength Indicators (RSSI). The Rx dynamic range is 70dB. Current consumption for TX and RX is 70mA and 50mA, respectively. The wake-up mode current is consumed 3.6 uA.
Wake-up sensitivity is -60dBm. The transceiver is implemented using the 1P8M 130-nm CMOS process and includes an ESD projection pad with a chip area of 3.5mm*3.5mm.
ACKNOWLEDGMENT
The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), Korea.
REFERENCES
[1] K. Kwon, J. Choi, J. Choi, Y. Hwang, K. Lee, and J. Ko,
“A 5.8 GHz integrated CMOS dedicated short range communication transceiver for the Korea/Japan electronic toll collection system,” IEEE Trans. Microw.
Theory Tech. vol. 58, no. 11, pp. 2751–2763, 2010.
[2] S. Moazzeni, M. Sawanm, and Glenn E.R. Cowan, “An Ultra-Low-Power Energy-Efficient Dual-Mode Wake- Up Receiver,” IEEE Trans. Circuits Syst. I Reg., vol. 62, no. 2, pp.517–526, Feb. 2015.
[3] T. Polonelli, T.L. Huy, L. Lizzi, F. Ferrero, and M.
Magno, “A wake-up receiver with ad-hoc antenna co- design for wearable applications,” in IEEE Sensors Applications Symposium, Catania, Italy, pp. 20–22, Apr.
2016.
[4] J. Blanckenstein, J. Klaue, and H. Karl, “A Survey of Low-Power Transceivers and Their Applications,” IEEE Circuits Syst. Mag., vol. 15, no. 3, pp. 6-17, thirdquarter 2015.
[5] Research Institute of Highway Ministry. Electronic Toll Collection-Dedicated Short-Range Communication- Part 1: Physical Layer; China Nat. Standard GB/T 20851.1-2007, Research Institute of Highway Ministry:
Beijing, China, 2007.
[6] H. Liu, X. Qu, L. Cao, R. Liu, Y. Zhang, M. Zhang, X.
Li, W. Wang, and C. Lu, “A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETC”
in IEEE Asia and South Pacific Design Automation Conference, Jeju, Korea, pp. 22–25, Jan. 2018.
[7] Noboru Sasho et al., “Single-chip 5.8GHz DSRC transceiver with dual-mode of ASK and Pi/4-QPSK,” in IEEE Radio and Wireless Symposium, Orlando, FL, USA, pp. 22–24, Jan. 2008.
[8] J. Choi, I-Y. Lee, K. Lee, S-O. Yun, J. Kim, J. Ko, G.
Yoon, S-G. Lee, “A 5.8-GHz DSRC transceiver with a 10-µA interference-aware wake-up receiver for the Chinese ETCS,” IEEE Trans. Microw. Theory Tech. vol.
62, no. 12, pp. 3146–3160, Dec. 2014.
[9] W. Zhu, D. Zhang, T. Gao, et al. “A 2.1 µA wake-up circuit for Chinese ETC system,” Journal of Electronics (China) 30, 308–312 (2013).
[10] A.S. Rekhi and A. Arbabian, “A 14.5mm2 8nW
−59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications,”
in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 11–15, Feb. 2018.
[11] T. Masuda et al., “Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS,” in IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, USA, pp. 96-449, Feb. 2002.
[12] S. J. Marinkovic and E. M. Popovici, “Nano-Power Wireless Wake-Up Receiver with Serial Peripheral Interface,” IEEE Journal on Selected Areas in Communications, vol. 29, no. 8, pp. 1641–1647, Sep.
2011.
[13] P. Kolinko and L. E. Larson, “Passive RF receiver design for wireless sensor networks,” in IEEE/MTT-S International Microwave Symposium, Honolulu, HI, USA, pp. 3–8 Jun. 2007.
[14] N. M. Pletcher, S. Gambini, and J. M. Rabaey, “A 52 μ W Wake-Up Receiver with − 72 dBm Sensitivity Using an Uncertain-IF Architecture,” IEEE J. Solid State Circuits, vol. 44, no. 1, pp. 269–280, Jan. 2009.
[15] S. Shin, S. Yun, S. Cho, J. Kim, M. Kang, W. Oh, S-M.
Kang, “18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power,” in IEEE International Symposium on Circuits and Systems, Seattle, WA, pp. 18–21, Mar. 2008.
[16] S. Drago, D. M. W. Leenaerts, F. Sebastiano, L. J.
Breems, K. A. A. Makinwa and B. Nauta, “A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 7–11, Feb. 2010.
[17] N. Pletcher, S. Gambini, and J. Rabaey, “A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodes,” in IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, pp. 16–19 Sep. 2007.
[18] K. -W. Cheng, X. Liu, and M. Je, “A 2.4/5.8 GHz 10 μW wake-up receiver with −65/−50 dBm sensitivity using direct active rf detection,” in IEEE Asian Solid- State Circuits Conference (ASSCC), Kobe, Japan, pp.
12–14 Nov. 2012.
[19] X. Huang, S. Rampu, X. Wang, G. Dolmans, and H. de Groot, “A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 7–1,1 Feb. 2010.
[20] P. Kamalinejad, K. Keikhosravy, M. Magno, S.
Mirabbasi, V. C. M. Leung, and L. Benini, “A high- sensitivity fully passive wake-up radio front-end for wireless sensor nodes,” in IEEE International Conference on Consumer Electronics, Las Vegas, NV, USA, pp. 10–13, Jan. 2014.
[21] D. Khan et al., “An Efficient Reconfigurable RF-DC
Converter with Wide Input Power Range for RF Energy Harvesting,” IEEE Access, vol. 8, pp. 79310–79318, 2020.
[22] D. Khan et al., “A CMOS RF Energy Harvester with 47%
Peak Efficiency Using Internal Threshold Voltage Compensation,” IEEE Microwave and Wireless Components Letters, vol. 29, no. 6, pp. 415-417, Jun.
2019.
[23] I. Demirkol, C. Ersoy, and E. Onur, “Wake-up receivers for wireless sensor networks: Benefits and challenges,”
IEEE Wireless Commununication, vol. 16, no. 4, pp. 88–
96, Aug. 2009.
[24] J. Choi, K. Lee, S. -O. Yun, S. -G. Lee and J. Ko, “An interference-aware 5.8GHz wake-up radio for ETCS,” in IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 446–448, Feb. 2012.
[25] I. Ali, B.S. Rikhan, D.-G. Kim, D.-S. Lee, M.R.U.
Rehman, H. Abbasizadeh, M. Asif, M. Lee, K.C. Hwang, Y. Yang, K.-Y Lee, “Design of a Low-Power, Small- Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology,” Sensors 2018, 18, 1555.
[26] N. Chabini, I. Chabini, E. M. Aboulhamid, and Y.
Savaria, “Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages,” IEEE Trans. Comput. Aided Des.
Integr. Circuits Syst. Vol. 22, no. 3, pp. 346–351, Mar.
2003.
[27] J. Lim, K. Lee, and K. Cho “Ultra low power RC oscillator for system wake-up using highly precise auto- calibration technique,” in IEEE European Solid-State Circuits Conference (ESSCIRC), Seville, Spain, pp. 14–
16, Sep. 2010.
[28] I. Ali et al., “An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop with Gain Estimation and Constant Current DCO,” IEEE Access, vol. 8, pp.
97215–97230, 2020.
[29] H. Abbasizadeh et al., “260-μW DCO with Constant Current over PVT Variations Using FLL and Adjustable LDO,” IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 65, no. 6, pp. 739-743, Jun. 2018.
[30] K. -W. Cheng and S. -E. Chen, “An Ultralow-Power Wake-Up Receiver Based on Direct Active RF Detection,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 7, pp. 1661-1672, Jul.
2017.
[31] P. M. Furth, Y. -C. Tsen, V. B. Kulkarni, and T. K.
Poriyani House Raju, “On the design of low-power CMOS comparators with programmable hysteresis,” in IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, USA, pp. 1–4, Aug. 2010.
Yeon Jun Kim received his B.S. degree from the Department of Electrical Engineering at Sungkyunkwan University, Suwon, Korea, in 2022. He is currently working toward the M.S. course in Electronics and Computer Engineering from Sungkyunkwan University, Suwon, Korea. His research interests include LNA and Switch.
Jae Hyung Jung received his B.S.
degree from the Department of Electrical Engineering at Kookmin University, Seoul, Korea, in 2022.
He is currently working toward the M.S.
course in Electronics and Computer Engineering from Sungkyunkwan University, Suwon, Korea. His research interests include PLL.
Tae Seob Oh received his B.S.
degree from the Department of Mathematics at Sungkyunkwan University, Suwon, Korea, in 2020.
He is currently working toward the M.S. course in Electronics and Computer Engineering from Sungkyunkwan University, Suwon, Korea. His research interests include DAC and Analog filter.
Jae Bin Kim received his B.S.
degree from the Department of Electrical Engineering at Myongji University, Suwon, Korea, in 2019.
Since then he has been working toward the combined Ph.D. & M.S.
Course in electronics and computer engineering from Sungkyunkwan University, Suwon, Korea. His research interests include RF Energy Harvesting and Wireless Power Transfer System.
Jong Wan Jo received his B.S.
degree from the Department of Electronic Engineering at Cheongju University, Cheongju, Korea, in 2018. He is currently working toward the M.S degree in School of Information and Communication Engineering, Sungkyunkwan University.
His research interests include Wireless Power Transfer systems and Power Management IC.
Kang Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively
From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose, CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of Information and Communication Engineering, Sungkyunkwan University, where he is currently a Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.
