Essential Results and Equations - SETASIGNThis e-book

SETASIGNThis e-book

Chapter 9 Essential Results and Equations

This final chapter of the book is a summary of the most important results and equations presented in the previous chapters. It is intended to serve as a reference guide which will - hopefully - provide a quick overview of principles and equations frequently used when designing analog CMOS circuits. References are given to the text in the preceding chapters where details can be found.

9.1 Design methodology Design phases:

The design process includes both analytical methods using math and calculations by hand and circuit simulation by computer.

Also implementation and evalua- tion by measurements is part of the design process, but this is not cov- ered by the present book.

Simulation methods in LTspice:

Dc operating point.

‘.op’

This command calculates an operating point and the small- signal transistor parameters in the operating point using nonlinear circuit equations. The small-signal parameters are listed in the error log file, opened by ‘Ctrl-L’.

Dc sweep.

‘.dc’

This command computes dc currents and voltages over a range of values for one, two or three independent current sources or voltage sources.

Transient analysis.

‘.tran’

This command computes currents and voltages as a function of time in a circuit with one or more sources specified as time- varying sources.

Dc transfer analysis.

‘.tf’

This command computes the small-signal input resistance, small-signal output resistance and transfer function from an (independent) input source to an output at a frequency of 0 Hz.

Ac analysis.

‘.ac’

This command computes the small-signal ac behavior of the circuit linearized about its dc operating point. This is used for find- ing the frequency response of a circuit, e.g., the Bode plot of a

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Fundamental principles:

The two fundamental theorems in circuit analysis are:

Kirchhoff’s current law (KCL), see Chapter 2.3.

The algebraic sum of currents flowing into a node equals zero.

Kirchhoff’s voltage law (KVL), see Chapter 2.3.

The algebraic sum of voltages across circuit elements connected in a closed loop equals zero.

Additional methods:

Methods for simplifying linear circuits:

Thévenin equivalent circuit, see Chapter 2.3.

A linear two-terminal circuit consisting of impedances, voltage sources and current sources can be replaced by an equivalent circuit consisting of an independent voltage source in series with an impedance.

Norton equivalent circuit, see Chapter 2.3.

A linear two-terminal circuit consisting of impedances, voltage sources and current sources can be replaced by an equivalent circuit consisting of an independent current source in parallel with an impedance.

Superposition, see Chapter 2.3.

In a linear circuit with more than one independent source, the total response is the sum of the responses to each of the independent sources acting alone with all other independent sources being reset.

Signal notation, see Chapter 2.1.

Time-domain notation, see Fig. 2.4:

Instantaneous value. Lowercase letter, uppercase subscript, e.g.,vA. Dc value or bias value. Uppercase letter, uppercase subscript, e.g.,VA. Ac value or small-signal value. Lowercase letter, lowercase subscript, e.g.,va. Amplitude. Uppercase letter, lowercase subscript, e.g.,Va. Frequency-domain notation:

Angular frequencyω. Uppercase letter, lowercase subscript, e.g.,Va(jω).

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CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

9.2 Device models, linear passive devices See Chapter 2.3.

Resistor Capacitor Inductor

Diagram symbol.

Time domain. v(t) =Ri(t) i(t) =Cdv(t)

dt v(t) =Ldi(t) dt

Frequency domain. V(s) =RI(s) I(s) =sCV(s) V(s) =sL I(s)

9.3 Device model, pn diode See Chapter 3.1.

Diagram symbol.

Shockley diode model,

see Chapter 3.1. ID=ISexp

nVT −1

ISexp

nVT

forVDVT =kT q .

Small-signal model. rd=

∂iD

∂vD

₋1

nVT

9.4 Small-signal models

A small-signal model is a linearized model of a nonlinear device equation, see Chapter 3.5. The small- signal parameters are calculated as partial derivatives in a specific bias point (operating point). Example:

Small-signal parameters:

gm= ∂iD

∂vGS

_bias

point

gds= ∂iD

∂vDS

_bias

point

=1/rds

Nonlinear large-signal model Linear small-signal model

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

9.5 Device models, MOS transistors

Diagram symbol,

NMOS transistor, see Chapter 3.3.

Diagram symbol,

PMOS transistor, see Chapter 3.3.

Transistor parameters. Threshold voltageVt, positive for NMOS transistors, negative for PMOS transistors.

Channel widthW. Channel lengthL. Channel-length modulation parameterλ, inversely proportional toL.

Electron mobilityµn(NMOS transistors).

Hole mobilityµp(PMOS transistors).

Gate capacitance per unit areaCox.

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CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Nonlinear device models for an NMOS transistor:

Shichman-Hodges transistor model, see Chapter 3.3.

Cut-off region:vGS≤Vt: iD=0

Triode region: 0≤vDS≤vGS−Vt: iD=µnCox

[(vGS−Vt)vDS−v²_DS/2](1+λvDS) Active region (saturation region): 0≤vGS−Vt ≤vDS: iD= µnCox

(vGS−Vt)²(1+λvDS)

Simplified Shichman-Hodges transistor model without channel- length modulation,

see Chapter 3.3.

Using 1+λvDS1 is often a reasonable approximation for hand calculations.

Cut-off region,vGS≤Vt: iD=0

Triode region: 0≤vDS≤vGS−Vt: iD=µnCox

[(vGS−Vt)vDS−v²_DS/2]

Active region (saturation region): 0≤vGS−Vt ≤vDS: iD= µnCox

(vGS−Vt)²

Body effect, change in threshold voltage when source and bulk are not connected,

see Chapter 3.3.

Vt=Vto+γ(

vSB+|2ΦF| −

|2ΦF|)

whereVto is the threshold voltage with vSB =0, γ is the bulk threshold parameter (or body effect constant) and |ΦF|is the Fermi potential of the body.

The voltage(vGS−Vt) is called the overdrive voltage,vov, or the effective gate voltage,veff, because it is the voltage effectively available for creating the channel beneath the gate electrode, see Chapter 3.3.

It is also called the saturation voltage,vDSsat, because it is the border between the triode region and the saturation region (active region) for the transistor characteristics, see Chapter 3.3.

The nonlinear device equations for a PMOS transistor are the same as for an NMOS transistors, provided absolute values forvGS−Vt,vDSandvSBare used andµnis replaced byµp, see Chapter 3.3.

For a PMOS transistor, the body effect causesVt to be more negative thanVto.

For a PMOS transistor in the active region, vGS−Vt is negative andvDSis more negative thanvGS−Vt, i.e., 0≥vGS−Vt ≥vDSand 0≤ |vGS−Vt| ≤ |vDS|. For a PMOS transistor in the triode region,vGS−Vt

is negative andvDSis negative, but less negative thanvGS−Vt, i.e., 0≥vDS≥vGS−Vt and 0≤ |vDS| ≤

|vGS−Vt|.

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Low-frequency small-signal model in the active region:

Small-signal diagram, see Chapter 3.5.

The small-signal model is the same for NMOS and PMOS transistors.

Transconductancegm, see Chapter 3.5. The equations are the same for NMOS and PMOS transistors, but for PMOS transistors you must use absolute values ofVGS−Vt and VDSand replaceµnbyµp.

gm= ∂iD

∂vGS = µnCox

(VGS−Vt)(1+λVDS)

= 2ID

VGS−Vt

2µnCox

ID(1+λVDS)

Approximate expressions forgm

using 1+λVDS1 which is often a reasonable approximation for hand calculations, see Chapter 3.5.

For PMOS transistors, use|VGS−Vt|andµp.

gm = 2ID

VGS−Vt

µnCox

(VGS−Vt)

2µnCox

Output conductancegds, output resistancerds=1/gds, see Chapter 3.5.

For PMOS transistors,

use|VDS|and|VGS−Vt|andµp. Using 1+λVDS1 is often a reasonable approximation for hand calculations.

gds=1/rds= ∂iD

∂vDS = λµnCox

(VGS−Vt)²

= λID

1+λVDS

λID

Bulk transconductancegmb, see Chapter 3.5.

For PMOS transistors, use|VSB|.

gmb= ∂iD

∂vBS = gm γ 2

VSB+|2ΦF|

Low-frequency figure of merit, intrinsic voltage gainAvi, see Chapter 3.5.

Avi= gm

gds =2(1+λVDS)

λ(VGS−Vt) 2 λ(VGS−Vt)

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CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

High-frequency small-signal model in the active region:

High-frequency small-signal diagram, see Chapter 3.5.

The small-signal model is the same for NMOS and PMOS transistors.

Gate-source capacitanceCgs, see Chapter 3.5.

Oxide capacitance.Cgs(2/3)W LCox. An overlap capacitance proportional to channel width may be added.

Gate-drain capacitanceCgd, see Chapter 3.5.

Overlap capacitance. Proportional to channel width.

NormallyCgdCgs. Gate-bulk capacitanceCgb,

see Chapter 3.5.

Overlap capacitance. Proportional to channel length.

NormallyCgbCgs. Bulk-source capacitanceCbs,

see Chapter 3.5.

Junction capacitance, approximately proportional to area of source diffusion.

Bulk-drain capacitanceCbs, see Chapter 3.5.

Junction capacitance, approximately proportional to area of drain diffusion.

Bulk/well-substrate capacitance Cbsub, see Chapter 3.5.

Junction capacitance, approximately proportional to area of well diffusion.

High-frequency figure of merit, unity-gain frequency fT of small- signal current gain,

see Chapter 3.5.

fT gm

2πCgs 3µ(VGS−Vt) 4πL²

Typical Shichman-Hodges transistor parameters for a generic 0.18 µm CMOS process. Note thatλ must be calculated according to channel-length fromλ =λ/L, see Chapter 3.3.

Parameter: µCox Vto λ =λL γ |2ΦF|

NMOS: 180 µA/V² 0.40 V 0.10 µm/V 0.5√

V 0.7 V

PMOS: 45 µA/V² −0.42 V 0.14 µm/V 0.5√

V 0.7 V

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

9.6 Basic gain stages at low frequency General amplifier model with a

voltage-controlled voltage source, see Chapter 4.

Small-signal parameters:

Open-circuit voltage gainAvoc. Input resistancerin.

Output resistancerout.

Small-signal voltage gainAvwith a load resistorRL: Av= vo

vin =Avoc RL

RL+rout

Small-signal voltage gainAvswith a load resistorRL

and a signal source resistorRS: Avs=vo

vs =Avoc

RL+rout

rin

RS+rin

Common-source stage with ideal bias current source,

see Chapter 4.1.

Small-signal equivalent for the common-source stage.

Input resistancerin. rin=∞ Output resistancerout. rout=rds1

Open-circuit voltage gainAvoc. Avoc=−gm1rds1

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CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Common-drain stage (source follower) with ideal bias current source and no bulk effect, see Chapter 4.2.

Small-signal equivalent for the common-drain stage.

Input resistancerin. rin=∞ Output resistancerout. rout= 1

gm1 rds1= rds1

1+gm1rds1 1 gm1

Open-circuit voltage gainAvoc. Avoc= gm1rds1

1+gm1rds1

Common-drain stage (source follower) with ideal bias current source and bulk effect, see Chapter 4.2.

Small-signal equivalent for the common-drain stage.

Input resistancerin. rin=∞ Output resistancerout. rout= 1

gm1+gmb1 rds1= rds1

1+ (gm1+gmb1)rds1 1 gm1+gmb1

g r g

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Common-gate stage with ideal bias current sources and bulk effect, see Chapter 4.3.

The coupling capacitors in the diagram are considered ideal dc open circuits and ideal ac short circuits.

Small-signal equivalent for the common-gate stage, including a source resistorRSand a load re- sistorRL.

Input resistancerin.

Note thatrin depends onRL. rin= rds1+RL

1+ (gm1+gmb1)rds1 1

gm1+gmb1+ RL

(gm1+gmb1)rds1

Output resistancerout. Note thatrout depends onRS.

rout=RS+ (1+ (gm1+gmb1)RS)rds1

rds1+ (gm1+gmb1)rds1RS

Open-circuit voltage gainAvoc. Avoc=1+ (gm1+gmb1)rds1(gm1+gmb1)rds1

For a common-gate stage without bulk effect (i.e., bulk and source connected), use gmb=0 in the equations above.

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CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Cascode stage with ideal bias current source and bulk effect, see Chapter 4.3.

Small-signal equivalent for the cascode stage.

Input resistancerin. rin=∞

Output resistancerout. rout =rds1+ (1+ (gm2+gmb2)rds1)rds2

(gm2+gmb2)rds2rds1

Open-circuit voltage gainAvoc. Avoc=−(1+ (gm2+gmb2)rds2)gm1rds1

−gm1(gm2+gmb2)rds1rds2

Transconductance amplifier model for the cascode stage,

see Chapter 4.3.

gmgm1

rout(gm2+gmb2)rds2rds1

The cascode stage may alternatively be implemented with an NMOS/PMOS combination. This is called a folded cascode, see Chapter 4.3.

CMOS ANALOG IC DESIGN: FUNDAMENTALS ChaPter 9 – essentIal results and equatIons

Differential pair with

resistive load, see Chapter 4.3.

Input voltages. Differential input: vID=vG1−vG2

Common-mode input: vICM= (vG1+vG2)/2 vG1=vICM+vID/2

vG2=vICM−vID/2

Output voltages. Differential output voltage: vOD=vD1−vD2

Small-signal transistor parameters.

gm1=gm2

gds1=gds2; rds1=rds2

Small-signal differential gain. Ad=vod/vid=−(RDrds1)gm1; RD=RD1=RD2

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