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CMOS Analog IC Design: Fundamentals

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Nguyễn Gia Hào

Academic year: 2023

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The specification for phase margin, PM, places restrictions on the location of non-dominant poles and zeros in the opamp. The specification for the output voltage range places limits on the saturation voltage of the output transistors M6 and M7.

Figure 7.2: Transistor schematic of the noninverting opamp with feedback network and load capacitance.
Figure 7.2: Transistor schematic of the noninverting opamp with feedback network and load capacitance.

Bias Circuits, Bandgap References and Voltage Regulators

Several approaches can be taken to generate a current that is less dependent on the supply voltage. One method is to make the bias current depend on a gate source voltage rather than the supply voltage.

Figure 8.1: Bias current circuit with NMOS transistors. Notice the notation 1 : N for the scaling ratio of the current mirror M 1 - M 2 .
Figure 8.1: Bias current circuit with NMOS transistors. Notice the notation 1 : N for the scaling ratio of the current mirror M 1 - M 2 .

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Essential Results and Equations

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The stability of a system with feedback depends on the frequency response of the loop gainL(s).

For a second-order system with a dominant pole ωp1 with a much lower frequency than the non-dominant pole ωp2, the phase margin depends on the location of the non-dominant pole relative to the gain bandwidth product ωtl = L0ωp1 of the loop gain.

Diagram symbol.
Diagram symbol.

Appendix A

Answers to Multiple-Choice Tests

Appendix B

Answers to End-of-Chapter Problems

LTspice gives slightly larger values ​​of bias currents and transconductances due to the channel length modulation, which has been neglected in the hand calculations. The difference is due to the factor (1+λVDS), which has been neglected in the calculations.

Appendix C – Transistor Models

Index

Gambar

Figure 7.2: Transistor schematic of the noninverting opamp with feedback network and load capacitance.
Figure 7.9: Simulation showing g m versus W for a PMOS transistor with L = 1 µm using the BSIM3 transistor model.
Figure 7.10: Simulation showing g m versus W for an NMOS transistor with L = 1 µm using the BSIM3 transistor model.
Figure 7.11: Simulation of PMOS current mirror showing output current versus output voltage.
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