Performance Monitoring
3.6 Software Debug
3.6.6 HW Breakpoint Resources
• Instruction breakpoint
• BKPT instruction
The processor ignores vector traps during monitor mode.
When an exception occurs in monitor mode, the processor takes the following actions:
• Disables the trace buffer
• Sets DCSR.moe encoding
• Sets FSR[9]
• R14_abt = PC of the next instruction to execute + 4 (for Data Aborts) R14_abt = PC of the faulting instruction + 4 (for Prefetch Aborts)
• SPSR_abt = CPSR
• CPSR[4:0] = 0b10111 (ABORT mode)
• CPSR[5] = 0
• CPSR[6] = unchanged
• CPSR[7] = 1
• PC = 0xc (for Prefetch Aborts), PC = 0x10 (for Data Aborts)
During abort mode, external debug breaks and trace buffer full breaks are internally pended. When the processor exits abort mode, either through a CPSR restore or a write directly to the CPSR, the pended debug breaks will immediately generate a debug exception. Any pending debug breaks are cleared out when any type of debug exception occurs.
When exiting, the debug handler should do a CPSR restore operation that branches to the next instruction to be executed in the program under debug.
An instruction breakpoint will generate a debug exception before the instruction at the address specified in the ICBR executes. When an instruction breakpoint occurs, the processor sets the DBCR.moe bits to 0b001.
Software must disable the breakpoint before exiting the handler. This allows the break- pointed instruction to execute after the exception is handled.
Single step execution is accomplished using the instruction breakpoint registers and must be completely handled in software (either on the host or by the debug handler).
3.6.6.2 Data Breakpoints
IXP42X product line and IXC1100 control plane processors’ debug architecture defines two data breakpoint registers (DBR0, DBR1). The format of the registers is shown in Table 36.
DBR0 is a dedicated data address breakpoint register. DBR1 can be programmed for one of two operations:
• Data address mask
• Second data address breakpoint
The DBCON register controls the functionality of DBR1, as well as the enables for both DBRs. DBCON also controls what type of memory access to break on.
Table 35. Instruction Breakpoint Address and Control Register (IBCRx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IBCRx E
reset value: unpredictable address, disabled
Bits Access Description
31:1 Read / Write Instruction Breakpoint MVA
in ARM mode, IBCRx[1] is ignored
0 Read / Write IBCRx Enable (E) -
0 = Breakpoint disabled 1 = Breakpoint enabled
Table 36. Data Breakpoint Register (DBRx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBRx
reset value: unpredictable
Bits Access Description
31:0 Read / Write
DBR0: Data Breakpoint MVA DBR1:
Data Address Mask OR Data Breakpoint MVA
When DBR1 is programmed as a data address mask, it is used in conjunction with the address in DBR0. The bits set in DBR1 are ignored by the processor when comparing the address of a memory access with the address in DBR0. Using DBR1 as a data address mask allows a range of addresses to generate a data breakpoint. When DBR1 is selected as a data address mask, it is unaffected by the E1 field of DBCON. The mask is used only when DBR0 is enabled.
When DBR1 is programmed as a second data address breakpoint, it functions independently of DBR0. In this case, the DBCON.E1 controls DBR1.
A data breakpoint is triggered if the memory access matches the access type and the address of any byte within the memory access matches the address in DBRx. For example, LDR triggers a breakpoint if DBCON.E0 is 0b10 or 0b11, and the address of any of the 4 bytes accessed by the load matches the address in DBR0.
The processor does not trigger data breakpoints for the PLD instruction or any CP15, register 7, 8, 9, or 10 functions. Any other type of memory access can trigger a data breakpoint. For data breakpoint purposes the SWP and SWPB instructions are treated as stores - they will not cause a data breakpoint if the breakpoint is set up to break on loads only and an address match occurs.
On unaligned memory accesses, breakpoint address comparison is done on a word- aligned address (aligned down to word boundary).
When a memory access triggers a data breakpoint, the breakpoint is reported after the access is issued. The memory access will not be aborted by the processor. The actual timing of when the access completes with respect to the start of the debug handler depends on the memory configuration.
Table 37. Data Breakpoint Controls Register (DBCON)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M E1 E0
reset value: 0x00000000
Bits Access Description
31:9 Read-as-Zero / Write-ignored Reserved
8 Read / Write DBR1 Mode (M) -
0: DBR1 = Data Address Breakpoint 1: DBR1 = Data Address Mask 7:4 Read-as-Zero / Write-ignored Reserved
3:2 Read / Write
DBR1 Enable (E1) -
When DBR1 = Data Address Breakpoint 0b00: DBR1 disabled
0b01: DBR1 enabled, Store only
0b10: DBR1 enabled, Any data access, load or store 0b11: DBR1 enabled, Load only
When DBR1 = Data Address Mask this field has no effect
1:0 Read / Write
DBR0 Enable (E0) - 0b00: DBR0 disabled
0b01: DBR0 enabled, Store only
0b10: DBR0 enabled, Any data access, load or store 0b11: DBR0 enabled, Load only
On a data breakpoint, the processor generates a debug exception and re-directs execution to the debug handler before the next instruction executes. The processor reports the data breakpoint by setting the DCSR.MOE to 0b010. The link register of a data breakpoint is always PC (of the next instruction to execute) + 4, regardless of whether the processor is configured for monitor mode or halt mode.