TDI TDO
3.6.14 Downloading Code in ICache
3.6.14.4 Loading IC During Reset
Code can be downloaded into the instruction cache through JTAG during a processor reset. This feature is used during software debug to download the debug handler prior to starting an application program. The downloaded handler can then intercept the reset vector and do any necessary setup before the application code executes In general, any code downloaded into the instruction cache through JTAG, must be downloaded to addresses that are not already valid in the instruction cache. Failure to meet this requirement will result in unpredictable behavior by the processor. During a processor reset, the instruction cache is typically invalidated, with the exception of the following modes:
• LDIC mode — Active when LDIC JTAG instruction is loaded in the JTAG IR; prevents the mini instruction cache and the main instruction cache from being invalidated during reset.
• HALT mode — Active when the Halt Mode bit is set in the DCSR; prevents only the mini instruction cache from being invalidated; main instruction cache is invalidated by reset.
Figure 25. Format of LDIC Cache Functions
2 5
0 0 31
Invalidate IC Line
x 0 x x . . . Invalidate Mini IC
VA[31:5]
Load Main IC
VA[31:5]
.. . Data Word 0 Data Word 7
Load Mini IC and
(CMD = 0b010)
(CMD = 0b011)
- indicates first
- indicates last bit shifted in
bit shifted in 0 0
0
0 0 0 0
0
0 0 0 CMD 32
0
1 2 5
31 0
32
2 5
31 0
32 P P
During a cold reset (in which both a processor reset and a JTAG reset occurs) it can be guaranteed that the instruction cache will be invalidated since the JTAG reset takes the processor out of any of the modes listed above.
During a warm reset, if a JTAG reset does not occur, the instruction cache is not invalidated by reset when any of the above modes are active. This situation requires special attention if code needs be downloaded during the warm reset.
Note that while Halt Mode is active, reset can invalidate the main instruction cache.
Thus debug handler code downloaded during reset can only be loaded into the mini instruction cache. However, code can be dynamically downloaded into the main instruction cache. (refer to “Dynamically Loading IC After Reset” on page 123).
The following sections describe the steps necessary to ensure code is correctly downloaded into the instruction cache.
3.6.14.4.1 Loading IC During Cold Reset for Debug
The Figure 26 shows the actions necessary to download code into the instruction cache during a cold reset for debug.
Note: In the Figure 26 hold_rst is a signal that gets set and cleared through JTAG When the JTAG IR contains the SELDCSR instruction, the hold_rst signal is set to the value scanned into DBG_SR[1].
An external host should take the following steps to load code into the instruction cache following a cold reset:
1. Assert the Reset and TRST pins: This resets the JTAG IR to IDCODE and invalidates Figure 26. Code Download During a Cold Reset For Debug
Internal TRST
JTAG IR
RESET invalidates IC
Enter LDIC mode RESET does not affect IC TRST resets JTAG IR to IDCODE
IDCODE
set hold_rst signal clear hold_rst signal Reset Pin
RESET
RESET pin asserted until hold_rst signal is set
Processor branches hold_rst
hold_rst keeps internal reset asserted
SELDCSR SELDCSR
keep Halt Mode bit set clock 15 tcks after
Download code set Halt Mode bit
to address 0
LDIC wait 2030 tcks after Reset deasserted
last update_dr in LDIC mode
2. Load the SELDCSR JTAG instruction into JTAG IR and scan in a value to set the Halt Mode bit in DCSR and to set the hold_rst signal. For details of the SELDCSR, refer to “SELDCSR JTAG Register” on page 103.
3. After hold_rst is set, de-assert the Reset pin. Internally the processor remains held in reset.
4. After Reset is de-asserted, wait 2030 TCKs.
5. Load the LDIC JTAG instruction into JTAG IR.
6. Download code into instruction cache in 33-bit packets as described in “LDIC Cache Functions” on page 118.
7. After code download is complete, clock a minimum of 15 TCKs following the last update_dr in LDIC mode.
8. Place the SELDCSR JTAG instruction into the JTAG IR and scan in a value to clear the hold_rst signal. The Halt Mode bit must remain set to prevent the instruction cache from being invalidated.
9. When hold_rst is cleared, internal reset is de-asserted, and the processor executes the reset vector at address 0.
An additional issue for debug is setting up the reset vector trap. This must be done before the internal reset signal is de-asserted. As described in “Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)” on page 92, the Halt Mode and the Trap Reset bits in the DCSR must be set prior to de-asserting reset in order to trap the reset vector. There are two possibilities for setting up the reset vector trap:
• The reset vector trap can be set up before the instruction cache is loaded by scanning in a DCSR value that sets the Trap Reset bit in addition to the Halt Mode bit and the hold_rst signal; OR
• The reset vector trap can be set up after the instruction cache is loaded. In this case, the DCSR should be set up to do a reset vector trap, with the Halt Mode bit and the hold_rst signal remaining set.
In either case, when the debugger clears the hold_rst bit to de-assert internal reset, the debugger must set the Halt Mode and Trap Reset bits in the DCSR.
3.6.14.4.2 Loading IC During a Warm Reset for Debug
Loading the instruction cache during a warm reset may be a slightly different situation than during a cold reset. For a warm reset, the main issue is whether the instruction cache gets invalidated by the processor reset or not. There are several possible scenarios:
• While reset is asserted, TRST is also asserted.
In this case the instruction cache is invalidated, so the actions taken to download code are identical to those described in “Loading IC During Cold Reset for Debug”
on page 120
• When reset is asserted, TRST is not asserted, but the processor is not in Halt Mode.
In this case, the instruction cache is also invalidated, so the actions are the same as described in “Loading IC During Cold Reset for Debug” on page 120, after the LDIC instruction is loaded into the JTAG IR.
• When reset is asserted, TRST is not asserted, and the processor is in Halt Mode.
In this last scenario, the mini instruction cache does not get invalidated by reset, since the processor is in Halt Mode. This scenario is described in more detail in this section.
In the last scenario described above is shown in Figure 28.
As shown in Figure 27, reset does not invalidate the instruction cache because of the processor is in Halt Mode. Since the instruction cache was not invalidated, it may contain valid lines. The host must avoid downloading code to virtual addresses that are already valid in the instruction cache (mini IC or main IC), otherwise the processor may behave unpredictably.
There are several possible solutions that ensure code is not downloaded to a VA that already exists in the instruction cache.
Since the mini instruction cache was not invalidated, any code previously downloaded into the mini IC is valid in the mini IC, so it is not necessary to download the same code again.
If it is necessary to download code into the instruction cache:
1. Assert TRST.
This clears the Halt Mode bit allowing the instruction cache to be invalidated.
2. Clear the Halt Mode bit through JTAG.
This allows the instruction cache to be invalidated by reset.
3. Place the LDIC JTAG instruction in the JTAG IR, then proceed with the normal code download, using the Invalidate IC Line function before loading each line.
This requires 10 packets to be downloaded per cache line instead of the 9 packets described in “LDIC Cache Functions” on page 118
Figure 27. Code Download During a Warm Reset For Debug
Internal TRST
SELDCSR JTAG IR
enter LDIC mode RESET does not affect Mini IC (Halt Mode Bit set)
JTAG INSTR SELDCSR LDIC
set hold_rst signal clear hold_rst signal
RESET Reset pin
RESET pin asserted until hold_rst signal is set
hold_rst
hold_rst keeps internal reset asserted
Halt Mode
Load code into IC
clock 15 tcks after wait 2030 tcks after
Reset deasserted
last update_dr in LDIC mode
keep Halt Mode bit set keep Halt Mode bit set