This tutorial shows a few ways to import files to LTspice and export files from LTspice. The main file format for this is the SPICE Netlist which describes the circuit to the simulator. But also output files from simulations are available, see for instance Fig. 1.15, and we have seen already in Tutorial 3 how model files can be imported to LTspice. After having completed the tutorial, you should be able to
– import a netlist file to LTspice and run simulations directly from the netlist.
– use a netlist input to define a subcircuit and create a symbol for the subcircuit.
– define a FinFET transistor symbol and model using both subcircuit and model files.
– export output netlist files from schematics.
– export output files from simulations.
Example 7.1: Importing a netlist file describing a current conveyor.
A current conveyor is a generic combination of a voltage follower and a current follower or current inverter. It is a three-terminal device with one input terminal, Y, one output terminal, Z, and one combined input-output terminal, X, see Fig. 7.1.
Figure 7.1:Current conveyor terminal definition.
The more popular form of the current conveyor is the second-generation current conveyor referred to as CCII (Sedra & Smith 1970). This device is described by the terminal relations
iY
vX
iZ
=
0 0 0
1 0 0
0 ±1 0
vY
iX
vZ
(7.1)
The definition incorporates a positive version and a negative version, corresponding toiZ=iX andiZ=
−iX, respectively.
Figure 7.2:CMOS current conveyor, CCII+.
Current conveyor netlist description.
Figure 7.3:Netlist description of the current conveyor from Fig. 7.2.
A simple CMOS implementation of a CCII+ current conveyor is shown in Fig. 7.2 (Bruun 1994), and a netlist corresponding to this schematic is shown in Fig. 7.3. In the schematic and in the netlist, nodes have been labeled by numbers. This is the original way of labeling nodes for Spice (Vladimirescu 1994).
However, with LTspice, you may use letters instead if you so wish.
The netlist file is named ‘ccii.net’ and can be opened in LTspice with the command ‘File→Open’ (or on the toolbar) using ‘Files of type: Netlists’. In LTspice, a simulation can be executed directly from the netlist file, but first the simulation must be specified. This is done by directly inserting the required SPICE directive in the netlist file. Also, the transistor model file (‘bsim3_035.lib’) must be included, and it should be in the same folder as the netlist file or in a folder to which a search path has been specified,
SPICE Netlist from the LTspice file editor.
Figure 7.4:SPICE Netlist for running a ‘.dc’ simulation of the current conveyor from Fig. 7.2.
Figure 7.4 shows the netlist file edited in LTspice to include model file, supply voltages, bias current, input signalsvX andiY, output loadRLand a simulation command for a dc sweep of the input currentiX. Also included is a ‘.end’ directive to mark the end of the netlist file. This is not required in order to run a simulation, but it is good practice to mark the end of the file, and when LTspice generates netlist files from a schematic, the ‘.end’ directive is also automatically inserted.
The simulation is run directly from the SPICE Netlist using the command ‘Simulate→Run’ or using the
‘Run’-symbol on the toolbar. Figure 7.5 shows the result of the simulation. The traces to be displayed are selected in the plot window using the command ‘Plot Settings→Add trace’ or the command ‘Plot Settings→ Visible Traces’. The command ‘Visible Traces’ is also available with the netlist window active (’View→ Visible Traces’) and on the toolbar, symbol . Figure 7.5 shows the input current iX and the output current iZ=−I(RL). The output current is almost the same as the input current as expected from Eq. (7.1).
Figure 7.5:Simulated output currentiZ=−I(RL)for the current conveyor from the SPICE Netlist shown in Fig. 7.4.
Example 7.2: Creating a subcircuit from a netlist.
The current conveyor is a generic building block in analog circuit design, so it is of interest to have it as a generic subcircuit with a symbol resembling the symbol shown in Fig. 7.1. For this, the netlist from Fig. 7.4 must be modified so that it starts with a ‘.subckt’ directive and ends with a ‘.ends’ directive.
Figure 7.6 shows the netlist with a minimum of changes required to turn it into a subcircuit specification.
SPICE Netlist, current conveyor subcircuit.
Figure 7.6: SPICE Netlist specifying the current conveyor as a subcircuit including transistor models, supply voltages and bias
The ‘.subckt’ directive and the ‘.ends’ directive have been inserted and the simulation command has been removed, but the file still contains both model specifications and specifications of supply voltages and bias current. The ‘.subckt’ directive specifies the name of the subcircuit and the order of the terminals.
(a) (b)
Figure 7.7:LTspice current conveyor symbol. Autogenerated from the netlist (a). Edited from the autogenerated symbol (b).
Next, we need a symbol for the subcircuit. This is achieved from the netlist editor by placing the cursor in the line ‘.subckt CCII 1 2 3’ and right-clicking. This opens a window where you can select ‘Create Symbol’ and answer ‘Yes’ in the dialogue window which opens. The auto-generated symbol is shown in Fig. 7.7(a). Using the symbol editor as described in Example 5.1, this is easily modified into the symbol shown in Fig. 7.7(b). When you save the symbol CCII.asy, it is by default saved in a folder for autogenerated LTspice symbols, ‘Documents\LTspiceXVII\lib\sym\Autogenerated’, so when in- serting the symbol in a schematic using ‘Edit→Component’ or hotkey ‘F2’, you must select the folder
‘[Autogenerated]’ in the component selection window, see Fig. 1.3. This folder remains unchanged when you install new versions of LTspice, so the symbols in the folder are not affected by LTspice updates.
You may also select to save the symbol in the same folder as your circuits using the symbol or in a dedicated folder for symbols to which a search path has been specified, see Fig. 3.11. The symbol includes a specification of the subcircuit netlist file (model file) from which it has been generated. This specification includes the full path to the model file. For portability of the symbol, it may be advantageous not to specify the full path but just the file name. In this case, LTspice will search for the file in the current folder and in the folders specified in the Library Search Path. This modification is accomplished using the command ‘Edit→Attributes→Edit Attributes’ (or ‘Ctrl-A’) which opens a ‘Symbol Attribute Editor’.
In this editor, you just change the file name in the line specifying the ‘ModelFile’.
Figure 7.8:LTspice schematic for running the same simulation as specified in the netlist in Fig. 7.4.
Figure 7.8 shows a schematic with the current conveyor symbol and input signals and load resistor. From this schematic, we can run the same simulation as the simulation run from the netlist file in Fig. 7.4, and the result is as shown in Fig. 7.5.
The subcircuit defined in Fig. 7.6 includes both a link to the transistor model file, the supply voltages and the bias current. For added flexibility, it may be desirable to have the specification of transistor models, supply voltages and bias current at the top level of the circuit hierarchy, similar to the Examples 5.1, 5.2 and 5.4. An easy way to achieve this is to specify the supply voltages and the bias current as parameters and omit the transistor model specification in the subcircuit.
SPICE Netlist, current conveyor subcircuit.
Figure 7.9: SPICE Netlist specifying the current conveyor as a subcircuit with supply voltages and bias current specified as parameters with default values.
Figure 7.9 shows the netlist file for this. In this netlist file, default values for the supply voltages and the bias current are specified. In order to override the default values, you must specify the parameters ‘VDD’,
‘VSS’ and ‘IB’ for the current conveyor symbol, rather than using a ‘.param’ SPICE directive. This is done by a right-click or ‘Ctrl-right-click’ on the current conveyor symbol. This opens the ‘Component Attribute Editor’ shown in Fig. 7.10, and new values for ‘VDD’, ‘VSS’ and ‘IB’ can be inserted in the
‘Value2’ line as shown in Fig. 7.10. Also mark the ‘Value2’ line to be visible in the schematic by inserting a ‘x’ in the rightmost column in the ‘Component Attribute Editor’.
Figure 7.10:Component Attribute Editor for specifying parameters for the current conveyor subcircuit.
Figure 7.11 shows the LTspice schematic including overriding parameter specifications and including the transistor model file. Also shown is a ‘.op’ simulation command. Running the ‘.op’ simulation, the bias conditions for the current conveyor can be verified if LTspice has been set up to save the subcircuit voltages and currents. This is done by the command ‘Tools→Control Panel’ where you select the tab
‘Save Defaults’. Here you tick ‘Save Subcircuit Node Voltages’ and ‘Save Subcircuit Device Currents’.
Figure 7.11:LTspice schematic for running simulations with specifications of subcircuit parameters.
In the specification of the supply voltages, you may use another parameter as shown in Fig. 7.12. Here, the numeric value of the supply voltage is defined as a parameter ‘Vsup’, and this parameter is stepped
Figure 7.12:LTspice schematic for running simulations with different values of supply voltage.
Figure 7.13:Simulation plot for the ‘.dc’ simulation specified in Fig. 7.12.
from 1.3 V to 1.7 V using a ‘.step param’ directive. Also the value of the load resistor has been changed to 20 kΩ. With this value of RL, the Z-output cannot deliver an output current of 100 µA because the output voltage exceeds the supply rails foriZ=±100 µA. This is shown in Fig. 7.13 where the output current is plotted versus the input current for three different values of supply voltage.
SPICE Netlist, current conveyor subcircuit with terminals for supply voltages and bias current.
Figure 7.14: SPICE Netlist specifying the current conveyor as a subcircuit with supply voltages and bias current connected to
An alternative way for specifying supply voltages and bias current at top level of the circuit hierarchy is by introducing terminals for the supply voltages and the bias current in the schematic symbol. This is achieved by first specifying the terminals in the netlist description as shown in Fig. 7.14 and then designing a symbol including these terminals in the same way as the symbol from Fig. 7.7.
Figure 7.15 shows a schematic with this definition of the conveyor symbol and with the bias current source replaced by a resistor which controls the bias current for the conveyor. With the resistor shown in Fig. 7.15, the bias current is about 1 µA for a supply voltage of±1.5 V.
Figure 7.15: LTspice schematic using a current conveyor symbol with supply voltages and bias current connected to separate terminals.
Example 7.3: Importing a FinFET transistor model from a netlist file and model files.
This example has been co-authored by Mir Muntasir Hossein, Graduate Student of Ahsanullah University of Science and Technology, Dhaka, Bangladesh.
A FinFET transistor is an example of a dual-gate MOS transistor. A basic FinFET structure is shown in Fig. 7.16 together with symbols for an n-channel FinFET and a p-channel FinFET. The channel region is created in a vertical fin on top of an insulating substrate by applying a voltage to gate electrodes on each side of the fin. The gray region between the green fin and the pink gate is the gate oxide. The FinFET may be modeled as a parallel connection of two MOS transistors where the gate of one of the transistors is called the front gate and the gate of the other transistor is called the back gate (Cao 2011).
Models for FinFETs can be found on Predictive Technology Website (2012). LTspice-compatible ver- sions of the files for 45 nm and 32 nm FinFETs dated Sep. 30, 2005 are based on BSIMSOI3.2 models which in LTspice are supported using the model parameter ‘Level=9’. In the LTspice web user group, LTspice-compatible model files can be found in ‘https://groups.io/g/LTspice/files/z_yahoo/Lib/FINFET’.
These files have been developed from the PTM-files by Dr. Mohammad A. Maktoomi (presently an Ass.
Prof. at University of Scranton, PA, USA) to be able to run with LTspice.
NMOS PMOS
Figure 7.16:The FinFET structure and symbols for dual-gate FinFET transistors.
In this example, we show how the files for 32 nm FinFETs can be used in LTspice and we show how dia- gram symbols for NMOS and PMOS FinFETs can be generated. The files needed to model the FinFETs are a netlist file defining the FinFET as a subcircuit consisting of two parallel-connected transistors (front gate transistor and back gate transistor) and model files for the front gate transistors and back gate tran- sistors. Thus, we have 5 files for defining the NMOS and PMOS FinFET transistors:
‘32nm_finfet.sp’: This file defines the subcircuits for an NMOS FinFET and a PMOS FinFET.
‘soinmos1.pm’: This file is the model file for the front gate NMOS transistor.
‘soinmos2.pm’: This file is the model file for the back gate NMOS transistor.
‘soipmos1.pm’: This file is the model file for the front gate PMOS transistor.
‘soipmos2.pm’: This file is the model file for the back gate PMOS transistor.
Netlist file defining subcircuits for n-channel FinFET and p-channel FinFET.
Figure 7.17 shows part of the file ‘32nm_finfet.sp’. In this file, two subcircuits are defined, one for the NMOS FinFET and one for the PMOS FinFET. Each of the subcircuits has references (‘.include’
directives) to two model files, one for the front gate transistor and one for the back gate transistor. Notice the two ‘.subckt’ directives, one for the NMOS transistor ‘DGNMOS’ and one for the PMOS transistor
‘DGPMOS’. In these directives, parameters defining the transistor geometries are introduced and default values are given. The channel length is defined by the parameter ‘ldg’ with a default value of 32 nm for both the NMOS and the PMOS. The channel width is defined by a parameter ‘wdg’ and from the netlist file, we notice that the channel width of the parallel-connected transistors ‘mn1/mn2’ and ‘mp1/mp2’ is
‘wdg/2’. For the NMOS transistor, the default value of ‘wdg’ is 80n, whereas for the PMOS transistor, it is 1u. The channel width of a FinFET transistor is related to the height of the fin forming the channel, so in practice, the channel width is not a parameter which can be controlled by the circuit designer and the default value of the channel width is likely to be the same for NMOS and PMOS transistors.
Consequently, in the following, we change the default value of ‘wdg’ for the PMOS transistor to be the same as for the NMOS transistor. However, what is available to the circuit designer is the option of defining an equivalent channel width by using transistors with multiple fins, effectively connecting more transistors in parallel. In order to facilitate this design option, we introduce a parameter ‘Fin’ for both the
‘DGNMOS’ and ‘DGPMOS’. The default value of ‘Fin’ is 1, corresponding to a transistor with a single fin. Thus, we redefine the parameter ‘wdg’ to be ‘wdg=Fin*80n’ so that the effective channel width is proportional to the number of fins. With these modifications, we have the netlist file shown in Fig. 7.18.
Netlist file defining subcircuits for n-channel FinFET and p-channel FinFET, including the fin count parameter ‘Fin’.
From the netlist file, we can generate FinFET symbols in the same way as described in Example 7.2 for the current conveyor. When the netlist file is opened with LTspice, the cursor is placed in the line containing the ‘.subckt’ directive. A right-click opens a window, where you can select ‘Create Symbol’
and answer ‘Yes’ in the dialogue window which opens. The auto-generated symbol for the DGPMOS is shown in Fig. 7.19(a). This symbol is saved in the folder with autogenerated symbols.
(a) (b)
Figure 7.19:LTspice symbol for the PMOS FinFET. Autogenerated from the netlist (a). Edited from the autogenerated symbol (b).
You may want to modify the symbol to resemble the symbol shown in Fig. 7.16. This is done using the symbol editor where you can delete the yellow rectangle and draw the symbol using the commands
‘Draw→Line’ and ‘Draw→Circle’ to draw the symbol and the command ‘Edit→Move’ to move the pins, labels and parameters to the appropriate positions. You may also select to hide the names of the pins in the symbol. This can be done by right-clicking on the pin in the symbol editor and selecting ‘Not Visible’ in the ‘Pin/Port Properties’ window. Also the parameters may be hidden by right-clicking on the text and selecting ‘Justification→(not visible)’ in the ‘Symbol Attribute’ window. If you wish to show some of the parameters when using the symbols in a schematic, this can be done in the same way as described in Example 4.1 and Fig. 4.3 for a MOS transistor. For the symbol for the DGPMOS transistor shown in Fig. 7.19(b), both the names of pins and the parameters ‘wdg’, ‘ldg’ and ‘Fin’ are hidden but the terminals are marked ‘FG’, ‘BG’, ‘S’ and ‘D’, simply by inserting the text using the command ‘Draw
→ Text’. Another modification which may be useful is a change of the path to the model file. In the autogenerated file, the full path to the model file ‘32nm_finfet.sp’ is given. For portability of the symbol, it may be advantageous not to specify the full path but just the file name. In this case, LTspice will search for the file in the current folder and in the folders specified in the Library Search Path, see Fig. 3.11.
This modification is accomplished using the command ‘Edit → Attributes → Edit Attributes’ which opens a ‘Symbol Attribute Editor’. In this editor, you just change the file name in the line specifying the
‘ModelFile’.
In the same way, a symbol for the DGNMOS transistor may be designed, see Fig. 7.20. The symbols are by default saved in the folder with autogenerated symbols but you may also save them in the folder with your FinFET circuits and the FinFET netlist and model files.
(a) (b)
Figure 7.20:LTspice symbol for the NMOS FinFET. Autogenerated from the netlist (a). Edited from the autogenerated symbol (b).
Simulating FinFET transistor characteristics: For the FinFET transistors, input and output charac- teristics may be simulated similarly to what has been shown in Example 3.3 and 3.4 for conventional pla- nar MOS transistors. As an example, we show transistor characteristics for an NMOS dual-gate FinFET.
The LTspice schematic for the simulations is shown in Fig. 7.21. In this figure, the parameter ‘Fin’ is visible. This is achieved by a right-click on the transistor symbol, opening a ‘Component Attribute Edi- tor’. Using this editor, the parameters ‘wdg’ and ‘ldg’ are moved from ‘SpiceLine’ to ‘SpiceLine2’ and in the right column (‘Vis.’) an X is inserted in the line for ‘SpiceLine’, compare Fig. 4.3 in Example 4.1.
Figure 7.21:LTspice schematic for simulating characteristics for a dual-gate NMOS FinFET.
In the schematic, the back gate is controlled by an arbitrary behavioral voltage source ‘B1’. With
‘V=v(VFG)’ as shown in Fig. 7.21, the back gate voltage is equal to the front gate voltage. With the voltage source ‘B1’ specified to be ‘V=0’, a simulation may be run where the back gate is grounded. We may start by simulating the characteristics with the input voltageVG connected to both the front gate (FG) and the back gate. The simulation directive shown in Fig. 7.21 result in the input characteristics for the transistor, i.e., the drain current versus the gate-source voltage for different values of drain-source voltage. In order to find the drain current, a voltage source ‘Vsense’ with a value of 0 is inserted in series with the drain. Thus, the drain current is ‘i(Vsense)’.
When starting the simulation, you may encounter a pop-up window prompting you to select saved wave- forms. Just select all and click OK. Alternative, include a directive ‘.save v(*) i(*)’ in the schematic to avoid the prompt window from opening.