Inspecting the Board ..2-1 Installing the Quartus Prime Design Software Subscription Edition ..2-1 Activating Your License ..2-3 Installing the Altera SoC Embedded Development Kit (EDS) ..2-3 Development Kits Installer.. 2-4 Installing the USB-Blaster Driver. This document describes the hardware features of the Arria® 10 SoC development board, including detailed pin-out and component reference information required to create custom FPGA designs that interface with all board components. The Arria 10 SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, logic-intensive designs using Altera's® Arria 10 SoC.
The board offers a wide range of peripherals and memory interfaces to facilitate the development of Arria 10 SoC models. Altera assumes no responsibility or liability arising from the application or use of any information. For more information about the Arria 10 SoC family of devices, refer to the Arria 10 SoC documentation support page.
Altera assumes no responsibility or liability arising from the application or use of any information, product or service described herein, except as expressly agreed in writing by Altera. To install the Altera Development Tools, download the Quartus Prime Pro Edition software from the Quartus Prime Pro Edition page in the Download Center of the Altera website.
Activating Your License
Installing the Altera SoC Embedded Development Suite (EDS)
Development Kit Installer
Installing the USB-Blaster Driver
SD Card Image with Example Software
Development Board Setup 3
Applying Power to the Board
Default Switch and Jumper Settings
Board Test System 4
BTS can be used to test board components, change functional parameters, observe performance and measure power consumption. While using BTS, you repeatedly reconfigure the FPGA with test plans specific to the functionality you are testing. The Configuration menu identifies the appropriate design to transfer to the FPGA for each tab.
After successfully configuring the FPGA, the appropriate tab appears that allows you to exercise the relevant features of the board. The board's test system and power monitor share the JTAG bus with other applications such as the Nios II debugger and. Note: Because BTS is designed based on the Quartus Prime programmer and system console, be sure to close other applications before using the BTS application.
Preparing the Board
Running the Board Test System
Using the Board Test System
Using the Configure Menu
The System Info Tab
Factory Test Version Indicates the version of the board test system currently running on the board.
The GPIO Tab
Push Button Switches Read-only control displays the current state of the table's user push buttons.
The XCVR Tab
PMA Setup Allows you to change the PMA parameters that affect the active transmitter interface. 1st pre—Specifies the amount of preemphasis on the pretap of the transmitter buffer. 2nd pre-determines the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
Post 1-Specifies the amount of pre-emphasis on the first touch of the transmitter buffer post. 2nd Post - Sets the amount of pre-emphasis on the 2nd tap of the transmitter's buffer post. DC Gain—Specifies the DC gain setting for the receiver's equalizer in four-stage mode.
Insert Error - Inserts a one-word error into the streaming data stream each time the button is clicked.
The PCIe Tab
The FMCA Tab
The FMCB Tab
The DDR3 Tab
Write, Read and Total Performance Bars – Show the percentage of the maximum theoretical data rate that the requested transactions are able to achieve. Write (MBps), Read (MBps) and Total (MBps) – Show the number of bytes of data analyzed per second. Insert Error—Inserts a one-word error into the transaction stream each time the button is clicked.
The DDR4 Tab
The Power Monitor
Power Information Displays root-mean-square (RMS) current, maximum and minimum numerical power readings in mA. Reset Clears the graph, resets the minimum and maximum values, and restarts the Power Monitor.
The Clock Control
Set New Frequency Sets the programmable oscillator frequency for the selected clock to the value in the target frequency control for the programmable oscillators. The Si5338 is capable of synthesizing four independent user-programmable clock frequencies up to 350 MHz and dial frequencies up to 710 MHz. Default Resets the frequency for the oscillator associated with the active tab to its default value.
Set New Freq Sets the programmable oscillator frequency of the selected clock to the value in the CLK0 to CLK3 controls for each Si5338.
Board Components 5
Board Overview
J24 JTAG chain header Allows access to the JTAG chain and disables the built-in USB-Blaster II using an external USB-Blaster cable. J22 Mini-USB header USB interface for FPGA programming and debugging through the built-in USB-Blaster II JTAG via a Type-B USB cable. SW1 Function Dip switch Selects I2C Master, controls PCIE slot power and selects FGPA image source.
LEDs are off when not in use or on when in use but idle. D20-D22 Program Select LED Illuminates to indicate which flash memory image is loaded into the FPGA when the program select button is pressed. The frequency can be programmed using a clock control GUI running on the MAX V CPLD 5M2210 system controller.
Bootable flash card options include QSPI flash card, micro SD flash card, and NAND flash card. FPGA connector memory card options include DDR3 HILO memory card and DDR4 HILO memory card. U5 Real-time clock DS1339 device with built-in power-sensing circuit that detects power outages and automatically switches to battery backup, keeping time even when the board is not powered on.
J35 Character LCD connector that plugs into the supplied 16 characters × 2 lines LCD module along with two spacers. SW5 On/Off switch Toggle to turn the board on or off when power is supplied from the DC input.
Featured Device: Arria 10 SoC
CPLD 5M2210 System Controller
4 M8 EXT_intn Input 3.3 V HPS External interrupt. low if PCIE_auxEn and PCIE_EN are not active.
FPGA Configuration
Reference Pin Name Pin Type I/O. 0_Reset after PCIE_En is enabled if the I/O MAX V function is disabled. connect I/O MAX V bit R16.
System Controller Configuration
FPGA Programming over On-Board USB-Blaster II
Note: If an external USB-Blaster (I/II) cable is plugged into the EXTERNAL JTAG KOOP, the MAX II automatically uses it as the master despite any DIP switch setting. The MAX II CPLD (EPM1270M256C4N) is dedicated only to the onboard USB-Blaster II function, which connects to the USB 2.0 PHY device on one side and outputs JTAG signals on the GPIO pins on the other side.
FPGA Programming by HPS
FPGA Programming by EPCQ Device
FPGA Programming over External USB-Blaster
Status Elements
Setup Elements
Board Settings DIP Switch
JTAG Chain Control DIP Switch
CPU Reset Push Button
Logic Reset Push Button
General User Input/Output
Character LCD
Clock Circuitry
On-Board Oscillators
Components and Interfaces
PCI Express
SoC Pin Name Schematic Signal Name Direction Description
10/100/1000 Ethernet (HPS)
Board Reference (U12) Schematic Signal Name Description Strapping Option 17 ENET_HPS_LED1_LINK PHY Address Bit 0 Pull High.
10/100/1000 Ethernet (FPGA)
HPS Shared I/O
Port (HPS)
The HPS USB interface is connected to the USB3320 PHY, which is connected to the micro-USB connector (J4).
RS-232 UART (HPS)
Real-Time Clock (HPS)
SFP+
I 2 C Interface
FPGA-I/O MAX V Interface
The LMK04828 controller sends the FT245RQ signals to the SPI interface of the LMK04828 clock cleaner chip. USB_MAXV_RXFn USB_MAXV_TXEn USB_MAXV_WR USB_MAXV_RDn USB_MAXV_RESET USB_MAXV_D0 USB_MAXV_D1 USB_MAXV_D2 USB_MAXV_D3 USB_MAXV_D4 USB_MAXV_D5 USB_MAXV_D6 USB_MAXV_D7.
HPS SPIO Interface
In transaction 1, a write instruction (I1) is sent with associated data, and the read data from a previous instruction is returned. In transaction 2, a write instruction (I2) is sent with associated data, and the read data from a previous instruction is returned. In transaction 1, a read instruction (I1) is sent and the read data from a previous instruction is returned.
In transaction 3, a write instruction (I2) with associated data is sent and the read data from I1 are returned. Because a 0 is a write, the read data register is not updated for the third transaction.
Memory
FPGA External Memory
HPS External Memory
HPS Boot Flash Interface
I 2 C EEPROM
Daughtercards
Board Power Supply
Power Distribution System
Power Measurement
Additional Information A
Board & User Guide Revision History
Compliance and Conformity Statements
CE EMI Conformity Caution
