The Effect Of Small Changes In Inverter DC Voltage On The Performance Of The Three-Level SSSC

Recall that in the case of the two-level SSSC, there is no change in the dead angle of the inverter, so the variable magnitude of ac compensating voltage is achieved by varying the dc voltage of the inverter. However, in the case of the three-level SSSC, the inverter dc voltage Vdc is fixed at 60kV (0.53 pu) and the dead angleyis varied to change the magnitude of the ac compensating voltages. This section has thus confirmed that despite this difference in control approach, the three-level stand-alone SSSC developed in this chapter is able to provide the same dynamic variation of compensating reactanceX_qas the stand-alone two-level SSSC of Sen, but with a fixed de voltage.

3.7 The Effect Of Small Changes In Inverter DC Voltage On The

The aim of this study is to show the time domain response from the dead angle calculator of the SSSC when the set point of the inverter's dc capacitor voltage is stepped down to a value that is too low to be able to support the ac voltage magnitude V_q associated with the required reactance (i.e. Xq*) demand. ^In practice, set point changes are unlikely to be made in a step fashion but rather by gradual ramping of the input from one set point to another. However, step changes are used in this study to observe the worst-case transient response. This study once again considers the three-level SSSC in the same transmission system considered by Sen in [34].

Fig. 3.16 shows the response of the three-level SSSC to such step changes; three system variables are shown, namely the desired dc voltage Vdc*, the actual measured dc voltage Vdc and the inverter dead angle y. At time t

=

0 ms, the required compensating reactance X_q

*

is 0.15 pu capacitive (i.e.X_q

* =

+0.15pu), the dc voltage is set at 60kV (0.53 pu) andyis controlled to stay at 23.5° by the dead angle calculator. At t

=

50ms, the desired dc voltage Vdc

*

is stepped down to 48kV (0.426 pu) i.e. a 20% decrease from the original dc value of 60kY. The voltage regulator rapidly reduces ^Vdc to try and meet the new commanded value, and in order to maintain the required magnitude of ac compensating voltage at this reduced value of inverter dc voltage, the dead angle calculator reduces the value of y. However, because the magnitude of ac compensating voltage V_q required is greater than can be supported by the inverter at this new value of V_{dc ,} the angleyreaches the lowest possible value (y=0°) at which time the angle yand inverter dc voltage enter a limit cycle. An expanded view ofyfrom 50ms to 150ms is shown in Fig. 3.16 (d) where the dead angle calculator within the controller outputs undefined values ofy (i.e. the value within the arc-cosine in Equation (3.25) is larger than 1). The actual dc voltage is also affected as a result of such fluctuation as shown in Fig. 3.16 (b).

From t = 150ms to t = 250ms, V_dc

*

is stepped back from an invalid operating point (where the system was in a limit cycle) to the original valid operating point where the system was originally at steady state i.e. V_dc

* =

60kY. Despite the fact that the system was in a limit cycle, when it is stepped back to a valid V_dc

*

it does recover (even after ymomentarily goes into the limit immediately after this step change ofV_dc*), although the system does take a long time to settle to a steady value ofy. When V_dc is stepped up further to 72kV (0.639 pu) at t=250 ms, i.e. a 20%

increase from the initial dc value, the dead angle calculator increases the value ofyto 39S to maintain the required V_q

*.

This shows that this particular increased dc voltage level also lies within the range of the dead angle calculator.

This study has shown that in the three-level SSSC, when the dc capacitor voltage set point value determined by the voltage regulator is not large enough, the output from the dead angle calculator

0.7 . - - - . - - - , - - - . - - - . - - - , - - - ; : - - - 1 0.65

0.6

0.5 0,45

0.40~---;;-0.~05;:---;:l0.71----;:0;-;.1~5---'0;!;.2,---'0:;-;.2~5'--'0:t.3;---'O~.35

0.7 0.65 0.6

~_Q)^0.55

c..

0.5 0,45

. .

f

^I

^ILMIW~

^,

80

0.05 0.1 0.15 0.2

Time (s)

(c)y

0.25 0.3 0.35

Cl 60

~Cl QJ

Cl

;- 40 0,c

~

20

°01--~t:.-'-L....U.-ll..J~~...tJ...J.!..JJ...Ll..~~--_;;l_;;__--_:::_::::=__--~:__---.Jq..Q5 0.3 0.35

(d)y

50

r'

- - - - , - - - , - - - r - - - r - - , . . - - - - , - - - , . . - - - - , ._ _-,-...:...:"'---,

.,

40

Q)

0,30QJ

e.

~20

~Cl

10

8.05 0.06

undefined angle

,

0.07

Fig.3.16: Time domain response of the three-level SSSCjollowing step change in Vdc*:

(a) Vdc*;(b) Vdc; (c) y, (d) expanded view oj yjrom O.OSs to 0.1Ss.

may be briefly undefined during a transient or, in a worse case scenario, the inverter de voltage may not even be sufficient to supply the required ac compensating voltage during steady state. It is therefore essential for the operator to adjust the desired dc voltage to a suitable level to ensure acceptable operation of the three-level

sssc.

The study has also shown that the system recovers satisfactorily by increasing the dc voltage after the dead angle 'Yenters a limit cycle for this particular case study. It is also noted that the actual dc voltage is properly regulated to follow closely the desired dc voltage, except during the limit cycle.

The next subsection considers the performance of the three-level SSSC and the response of the transmission system with the same required compensating reactance ofXq

* =

0.15pu capacitive, but with the desired dc voltage magnitudes V_dc

*

increased with respect to the ones chosen in this particular study to avoid the problem of limit cycle.

3.7.3 Time Domain Response Following Step ChangesInVdc* (Xq*=0.15 pu) - Second Case Study: Values OfyWithin Range

This subsection once again considers the time domain response of the SSSC and the transmission line when subjected to deliberate changes in the desired dc voltage Vdc*. The changes in Vdc

*

are of the same percentage magnitude as in the previous section, but the initial magnitude of the dc voltage, and each subsequent magnitude ofVdc , is increased by 18kY. (This overall increase in V_dc of 30% is done to ensure that the dc voltage values all lie within the dead angle calculator limits throughout the transient investigation.) Fig. 3.17 shows the response of the three-level SSSC and the transmission system following these changes in the amplitude of the inverter dc voltage.

As in the previous section, when time t

=

0 ms, in Fig. 3.17, the required compensating reactance X_q

*

is 0.15 pu capacitive (i.e. X_q

* =

+0.15pu), but now the dc voltage is set at 78kV (0.692 pu) and 'Y is controlled to stay at 44.2° by the dead angle calculator. At t

=

50ms, the desired dc voltage Vdc* is stepped down to 66kV (0.586 pu). The dead angle 'Y decreases and settles to around 33° to maintain the required fundamental magnitude of the ac compensating voltage Vq

*

injected into the line. This decrease in 'Y corresponds to an increase in the width of the on-pulse of each turn-off device, which causes a change in the shape of the ac compensating voltage waveform, e2a' The decrease in V_dc*, on the other hand, decreases the peak amplitude of the ac compensating voltage waveform, e2a, as shown in Fig. 3.17(d). However, the combination of reduced peak and increased width of on-pulse of the ac waveform ensures that its fundamental magnitude remains constant at steady state as required. The line currentia and both the active

(Pq) and reactive (Qq) powers are almost unchanged despite some small fluctuations immediately after the step change in V_dc*. This confirms that the required steady-state compensation provided by the three-level SSSC is unaffected by the change in the value ofVdc ' At t

=

150ms, V_dc

*

is stepped back up to 78kV andyreturns to 44.2° in steady state.

When V_dc

*

is stepped up further to 90kV (O.798pu) at t = 250ms, y increases to 51.7°. This increase in the desired dc voltage increases the peak amplitude of the ac compensating voltage ^e2a'

(a) V

dC•

0.9 0.8

'c

I

=:

^0.7

ID

I I

(l.

0.6

0.50 0.05 0.1 0.15 0.2 0.25 0.3 0.35

(b) V

dC

0.9 0.8

~

(

'c

=:

^0.7

ID

l ⁽

(l.

0.6

0.50 0.05 0.1 0.15 0.2 0.25 0.3 0.35

100

(c)y

ID 80

~Cl 60

ID

0

r

40 ^~-

~Cl

c 20

«

00 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Time(5)

Fig.3.l7: Time domain response of the three-level SSSC and the transmission system following step changes in Vdc*: (a) Vdc*; (b) V_dc; (c)

r

'(d)e 2a

0.51 ----,.----.---.,---=:.::...-...---,....---,---, o

'I I ^I ~ ~ ~ ~ ~ ~ t ^{I I I}

^{1 ,}}

^{I I i ~ I}

~

_-0.5;:'0⁰ ---,0;-;.O"'5----;;-l-;---;::-~---:-!'::---:-l:-,'^W

^{V V V V V V V ) V V}

^V

~ ^{V V}

^{,...--_ _}

^V

^V

^V

^{....L-_ _V V}-.J^'

0.1 0.15 0.2 0.25 0.3 0.35

(e)i

3r---..---r----,---.:...--.----,---.,..---.a

2

';::

=:> 0

Cl.:v

-1

~ ^r r f r ^r r r r r r r r ~ ^{r r r r r r}

-2

V

^v

V

^{V V}

v V

V

V

v v V V V v

V

v

V

v

V

-30;---r;-;;-~--;;_L;_---;::-.l;-;'_{0.05 0.1 0.15}::----:-l::---:-c:,."..---L---l_{0.2 0.25 0.3 0.35}

Time (s)

(f)Pq

2.5r---r----.----.,---.----,....---,.---,

2f - - - - . - J

:g ^1.5

=:>

~ ¹

0.5

00~--__;:;_;~--__;::_l_::__--:::_7:'::---;;.!'::__---=7::----~'-:----~0.05 0.1 0.15 0.2 0.25 0.3 0.35

(9) Oq

0 . - - - , . - - - , - - - , - - - . - - - - , . . . - - - - . . . . - - - ,

-0.2 -0.4

:g -0.6

=:>

£

^-0.8

~_ _--J

-1

-1.2

o 0.05 0.1 0.15 0.2

Time (s)

0.25 0.3 0.35

Fig.3.J7(continued): Time domain response of the three-level SSSC and the transmission system following step changes in Vdc*: (d) e2a; (e) ia;(f)Pq; (g) Qq.

The resulting increase in ymeans a decrease in the width of the on-pulse of each turn-off device, and therefore a change in the shape ofe2a as shown in Fig. 3.17(d). The line current ia and both the active (Pq) and reactive (Qq) powers still remain unchanged during steady state, confirming once again that the steady-state compensation is unaffected by the change in Vdc .

It is noted that during each change of V_dc*, there are transient periods before variables settle to their steady state values. As previously explained, this is due to the exchange of active power at the interface between the SSSC and the transmission line, in order to charge or discharge the inverter dc capacitor to the new desired voltage levels. However, during steady state these changes in the dc voltage do not change the variables on the ac side of the SSSC i.e. the ac characteristics of the transmission line remain unaffected by Vdc , provided that the chosen set point V_dc

*

is within the range of dead angle calculator. Therefore, within limit, the dc voltage may be controlled to vary the dead angle yand therefore adjust the total harmonic distortion (THD) to appropriate levels. The topic of varying dc voltage in regards to THD is to be investigated in the next section.

3.8 The Effect Of Small Changes In Inverter DC Voltage On The Total