DATA
7.2 Processing the DSP to Software Radio Stream
The data sent from the DSP card is formatted as a series of user bytes, each one stored in a time slot. Since there are 32 time slots, and only 16 users are supported by the system presently, the second half of the frame will be discarded. For the data bits to be chipped and sent appropriately. the stream needs to contain successive user bits, not bytes. Primarily, this is because the OSP system is not sufficiently pow~rful to format the data stream so as to hav~
successive user's bits making it up. The solution is to create a buffering entity that is also capable of re-ordering the received bits. Conversely, the process needs to be reversed when sending data back to the DSP system. Here, the sllccessive user's bits need to be constructed into successive user's bytes, allowing for the correct reception on the DSP board.
7.2.1 The Reorderin g Process
The reordering of the stream occurs in a dual array of bits. These two buffers, a storage buffer and a shipping buffer, are declared as long unsigned standard logic arrays. This allows for the implementation of rapid shift registers. The previous code fragment shows how the storage buffer is generated.
Chapter 7 Interfacing
1. if (SCLKx2'event and SCLKx2 = '0' ) then 2.
3. 4. 5.
if (BitCounter ShipBuffer tmpByteCounter PHYDataOut
511) then --we need to reset the counters
<- StoreBuffer:
6. else
7. tmpByteCounter 8. end if:
.... 1:
<= StoreBuffer(O) ;
;= ByteCounter:
9. if «BitCounter mod 2 = 1) and (BitCounter /= 511)) then 10.
11.
12. 13.
PHYDataOut <= ShipBuffer(tmpByteCounter tmpByteCounter ;= tmpByteCounter + 1; if (tmpByteCounter - 32) then
ShipBuffer <= ShipBuffer SRL 1;
14 . tmpByteCounter ;= 0:
15. end i f; 16. end if;
17. ByteCounter <= tmpByteCounter;
18. end if;
8) ;
This code fragment has exactly the same value for the BitCounter variable as in the previous fragment. However, to achieve the high level of synchronization, this process is clocked on the falling edge of the double-rate serial clock. Thus, as soon as the bit counter reaches a value of 511, and the storage buffer has been completely filled, it is copied to the shipping buffer (line 2- 3). At the same time, the first bit frol11 the storage buffer is placed on the data out (line 5).
Note that with VHDL, the signal assignment is only valid once the process is complete, and this is why the storage buffer is used to source this data bit, and not the shipping buffer (line 5).
Note also that, from the timing analysis, every odd falling edge of the double-rate serial clock corresponds to the beginning of a bit period. Thus, line 9 checks for this condition, while avoiding the first time this condition is true (when the bit counter is SI I). Lines 10 to IS achieve the re-ordering process. By referencing 8 times the current byte counter value in the shipping buffer, the next bit to be transmitted can be sent. Once all 32 time slots have been processed in this manner, the shipping buffer is shifted to the right (line 13), and byte counter is reset. This will occur for each of the 8 bits per time slot. In this manner, the input stream is mapped to the output stream:
2.G04IMbpo
~
Figure 7.3 - Bit-Level Transpose on Data Stream
53
Chapter 7 Interfacing
In Figure 7.3, only two byte are shown, where Bxy. is bit y of byte x. In this manner, the bits are shipped out of the cntity first in byte order (user 0 is sent first), and then in bit order (bit 0 of user 0 is sent first).
Th e Inverse Ofl/erillg Process
Before the user bits may be sent to the DSP, they need 10 be re-packed in user bytes. An entity not unlike the above-mentioned is employed for this task. However, the process is reversed so as to present the DSP with intelligible data.
7.2.2 Serial to Parallel Co nversion
A further facet of the interfacing procedure is to create an entity capable of extracting bytes and words from the serial data stream. This entity finds its use when dealing with a parameterised system. For instance, if the system is set up to generate A WON of a specific SNR, then the parameter would be the desired level oftbe noise. Another example is a 16-bit number where the individual bits are code-usage flags. In other words, if the bit is set, then the corresponding chipping code in the Chipping database must be enabled. These parameters may be conveniently encoded as bytes and words by the DSP and then transmitted serially to the software radio. To carry out the addition or multiplication with these parameters as inputs, the stream needs to undergo a serial 10 parallel conversion. Furthermore, the parallel data needs to be synchronous with the allocated SC-BUS time slots.
1. DOPacking: process (SCLK, fSYNCN)
2. variable tmpLocalByte : IEEE. numeric std.UNSIGNED(7 downto 0) ;
3. begin
4. if (SCLK'event and 5CLK - '0') then
5. if (fSYNCN = '0') OR (ByteCounter - "111") then 6.
7.
8.
9.
10.
11.
12.
ByteCounter <- "000";
e1sif (ByteCounter < "Ill") then
ByteCounter <- ByteCounter + "001";
end if;
tmpLocalByte : - Loca1Byte 5LL 1;
tmpLocalByte(O) :"" BitStream;
Loca1Byte <- tmpLocalByte;
13. end if;
14. end process;
15.
16. DoShipping: process(SCLK) 17. begin
18. if (SCLK'event and SCLK - '1' ) then 19. if (ByteCounter - "Ill'" then
Chapter 7 Interfacing
20. ByteCLK <= '] ';
21. ByteOut <= LocalByte;
22. elsif (ByteCounter .. "Oll") then 2 3 . ByteCLK <"" '0';
24. end if;
25. end if;
26. end process;
The entity responsible for packing the bytes is broken into two logical processes. This first accumulates the byte information, while the second, responding to the complementary clock edge, makes the constructed byte, along with a positive logic clock, available to other entities. Notice how line 5 once again achieves synchronism by resetting the main counter while the frame sync is low. Notice how, since the single rate serial clock is being used, the frame sync is low only once during a clock cycle, removing the need to avoid a second frame sync reset.
Once the bits have been shifted in, the rising clock edge is used to map the accumulated byte to the output port of the entity.