Chapter 6 System Overview
Until this point, this thesis has presented the reader with a fairly comprehensive background.
This has included both a theoretical study of spread spectrum communication techniques, balanced with a look at some of the practical issues relating to system implementation. With this background work, it is now possible to propose a practical communications system. This chapter will give a brief overview of the system functional blocks employed in such a system, while the subsequent chapters will delve into the intricacies of several of them. The blocks have been implemented on Alcatel Altech Telecomlll's flexible radio platform (introduced in section 4.3).
6.1 Th e System Block Diagram
This diagram is presented for the downlink of a practical COMA "ystelll employing digital transmitter and receiver filters, while employing Walsh codes and a suitable MM SE structure to resolve the channel information.
Personal Computer
Oata DSP 1'---' RS485 Software
Source/sink Subsystem 'v---> Subsystem Radio Subsystem
Figure 6.1 - The Project Block Diagram
Figure 6.1 shows the essential components of the overall system. This design has been adopted, since the Alcatel Altech Tclecomms engineering team instigated it. The Personal Computer acts as a data source/sink, giving the designer control over the nature of the data sent to the physical layer. The DSP is primarily responsible for packing the data correctly for the software radio. This includes framing and packing the data into bytes. A daughter card is responsible for converting the high·speed serial signals from the OSP subsystem to RS·485. The softvlare radio subsystem includes a corresponding RS-485 communications module. These two RS-485 conversion modules introduce a conversion delay that has fairly severe implications. Chapter 7 will deal further with the issues of interfacing the software radio subsystem and the OSP subsystem. However, the core of the implementation process deals with the elements within the software radio. Here, the CDMA physical layer is implemented.
47
Chapter 6 System Overview
Control FPGA
RS-485
~
Si-directionalr--,
WalshConversion Interface .-' Encoder
Module
Transmitter Filter
MMSE Bit· Pilot
~
Estimator Synchronisation
H 7
Pulse Receiver
Detector
<-
FilterProcessing FPGA
Figure 6.2 - Detailed System Block Diagram
Figure 6.2 outlines the main elements residing to the software radio. The bi-directional interface, connected to the RS-485 conversion module, is responsible for generating a variety of clock signals for the communications bus that exists between the software radio and the DSP subsystem. These signals allow for proper framing and timing within the DSP subsystem, and will be explained in great detail in Chapter 7. This interface also serves to buffer and correctly pack the data from the MMSE bit estimator and send it on to the DSP. The bi-directional interface is also responsible for unpacking the information received from the DSP subsystem and presenting it to the Walsh encoder in a suitable fonnat. This allows the Walsh encoder to chip the data for several users simultaneously and then superpose it. Chapter 8 will deal with the implementation of the Walsh encoder, introducing the idea of the code database as a
"storage and chipping" technique. Further, there are two filters included in the processing FPGA. 4.3, The Alcatel Altech Telecoms Flexible Radio Platform dealt with the support hardware that is included in the software radio used in this project. Unfortunately. while transmit mixers are included there is no comparable hardware to return a received signal to its base-band fonn. In fact, the original intent was for designers to incorporate a receiver mixer in thc software radio. Since this is outside the scope of this thesis, the transmitted signals are simply tied internally to the receiver filter. In Chapter 1I , this transmitted signal will be distorted with internally generated AWGN and Rayleigh fading before being joined to the receiver filter. Chapter 9 will examine both the transmilter and receiver filter in detail, showing how the software radio is useful for moving such filtering operations into the digital domain. Finite Impulse Response digital filtering techniques are employed to limit the signal
Chapter 6 System Overview
bandwidth, while suppressing inter-symbol interference and maximising the signal-ta-noise ratio at the input to the detector. The pulse detector entity is responsible for sampling the stream received from the receiver filter. This entity has its sample point controlled through a feedback decision made by the pilot synchroniser. The pulse detector is capable of shifting in timc to present a different set of sampled chips to the MMSE bit estimator. This estimator is responsible for accumulating these chips and processing them to produce the bit estimate.
Chapter 10 extends some of the theoretical information on multi-user detectors to the point of implementation, examining the limitations of an FPGA-only solution to the problem of detection. Included is a simple system for synchronising to a pilot signal, along with a performance analysis. Finally, in Chapter 11 , the system is subject to testing in a simulated channel environment. Here, additive white Gaussian noise and Rayleigh fading implementations are examined.
From this point onward, the reader will be exposed to more of the practical implementation issues associated with this type of CMDA system. Finally, the measured perfonnance of the system will be presented in the fonn of a conclusion.
49