100606212P, Session: October 2006 was accepted as satisfactory on December 28, 2008 in partial fulfillment of the requirement for the degree of MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONIC ENGINEERING. Tunnel barrier with voltage control and underlay is the transport physics of the device and dictates the performance of the device in both the off and on states. Underlap mainly affects the tunnel component of the current and therefore results in an improvement of the subthreshold regime of the transistors, while the deterioration of the on-state performance of the device is insignificant.
The effects of gate length on device performance have also been investigated. With the increase in gate length, the off-state current is reduced and the on-off ratio is improved, but the on-state performance of the device is degraded due to the increase in gate capacitance and reduction in transconductance. Therefore, appropriate selection of underlap, gate length, gate bias range, and gate metalworking function can optimize device performance in both off and on states.
Introduction
- Literature Review
- Scaling of Devices and Silicon Nanowire Tran- sistors
- Objective of the Work
- Organization of the thesis
Potential advantages of SiNWFETs over the planar state-of-the-art silicon devices have been investigated [7, 16]. This work is primarily concerned with the study of the performance of silicon nanowire transistor with source drain underlap. Several authors have previously attempted to study the effects of underlap on nanowire transistors, mostly using I-D or 2-D Poisson-Schrodinger solvers [20] and reported primarily on the subthreshold region of the transistor operation.
The off-state performance, such as on/off current ratio, transconductance, inverse subthreshold slope with underlap, was calculated based on the IV profile. The on-state performance, such as intrinsic gate delay and intrinsic cutoff frequency for different underlaps, has also been calculated. The off-state performance such as on/off current ratio, transconductance, inverse subthreshold slope and on-state performance such as intrinsic gate delay and intrinsic cutoff frequency for different gate lengths have also been calculated.
Methodology
2.1 3-D Poisson's Equation
Tight Binding Hamiltonian Formulism
The Schrodinger equation in 3D Cartesian coordinates is. 2.8) where,"ljJ is the wave function, mx, my, and mz are the effective masses in unit coordinates, and Ii is the reduced Planck's constant. Ballistic transport is assumed and the recursive Green's function algorithm (RGFA) [26,28] is used to solve the Schrodinger equation for charge density and current calculations The open boundary condition in transport direction (x) is included in the Schrodinger equation via self-energy matrices.
For RGFA, the layer (cross-section) Hamiltonian and layer-to-layer coupling matrices are calculated from the discretized Schrodinger equation. The left side of the Schrödinger equation can be represented in matrix form as. Where hOD and hll are the layer Hamiltonian and tOl and tlO are the layer-to-layer coupling matrix.
Non-equilibrium Green's Function
Self-consistent Solution
The nanowires under the gate region and the Lu submatches between the .doped n-type source and the Lex drain extension are undoped. The substrate oxide, gate oxide, and expanded oxide are assumed to be SiO2 with a dielectric constant value of 3.9. The Fermi source level is set to zero (0) and the Fermi drain level to -VDS.
The gate metal is assumed to have the same work function value as the nanowire. The convergence criterion of the system was set to a voltage difference of :S;1 mV for all grid points from the previous iteration.
Results and Discussions
I-V characteristics
The simulated logID - Vcs plots for six different values of the underlap are shown in Figure 3.2. In the figure we see both the off-current and the on-current decrease with the increase of the underlap. The data shows that while the on current decreases by about one order of magnitude, the off current decreases by almost three orders of magnitude. The on-state current for a 2 nm underlap has a tunnel component of 0.85/lA and a thermal component of 0.42/lA.
The off current, the on current, the on/off current ratio, and the inverse subthreshold slope (88) are plotted in Figure 3.5 as a function of source-drain underlap. Both the current and reverse subthreshold slopes decrease rapidly with Lu and then nearly saturate when Luis is around 6 nm. The off current and the on/off current ratio, on the other hand, do not show this behavior.
This is because the effect of overlap in the off-state is more significant than its effect in the on-state. The exponential fit to the simulated data for the off-stream and the on-stream. Note that the on/off current ratio of 1.5 x 105 without source-drain overlap is already a decent one.
The turn-on current with the bottom overlap drops below 1.0 I"A because a significant contribution to the turn-on current is the tunneling component (see discussion of Figure 3.3). This can be improved by extending the bias range or engineering the work function of the gate metal so that in in the on state, a flat band is obtained between the original Fermi level and the channel potential under the gate.From the figure, we see that the on current (for v;,s = 0.7 V) is of the same order for different gate lengths, but decreases drastically with length neck.
From the figure, we can see that the on-state currents for different lengths of gate 1 are of the same order, but the off-state currents decrease significantly with increased gate length. Changing the gate length from 5 nm to 10 nm improves the on/off ratio by three orders of magnitude and the inverse subthreshold slope from 141.68 mV/dec to 82.59 mV/dec. From the figure, we can see that in the off state, the height and width of the tunnel barrier for Lg = 10 nm are significantly higher than those for Lg = 5 nm, and therefore the tunnel current (the main component of the off state current) for Lg = 10 nm through the barrier is greatly reduced compared with that at Lg = 5 nm, while in the on state there is no significant difference in the potential barrier for these two different gate lengths, so the resulting on-state currents are of the same order of magnitude.
Performance Metrics
In Figure 3.12 we plot the switching delay in the on state and the intrinsic cutoff frequency in the on state with the gate bias. Although gate capacitance increases with gate bias, intrinsic gate delay decreases and intrinsic cutoff frequency increases with gate bias. In Figure 3.13 we plot the gate capacitance in the state and the frequency of the different components (Cb, C" and Cd) as a function of the overlap.
From the plot, we see that the on-state gate capacitance is reduced by under when all three of its components fall. Looking at the plot, we see that the on-state transconductance decreases with the increase of underlap. However, the inflow is also reduced with underlap, and the combined effect is an increase in switching delay.
We observe an improvement in the switching delay and cutoff frequency when the bias range is widened to achieve the fiat band of the source channel in the on state. The simulated gate capacitance versus gate length and transconductance versus gate length are shown in Figure 3.16. From the figure we see that the gate capacitance increases and the transconductance decreases with increased gate length.
For a change in gate length from 5 nm to 10 nm, the gate capacitance increases from 1.27 aF to 2.28 aF, while the conductance decreases from 99.3fJB to 64.2j.LS. The inherent switching delay versus gate length and the unity current gain frequency versus gate length are shown in Figure 3.17. It can be seen from the figure that both the intrinsic switching delay and the unity current gain frequency deteriorate with longer gate length.
To change the gate length from 5 nm to 10 nm, the intrinsic switching delay increases from 0.056 pica second to 0.23 pica second, and the unity current gain frequency decreases from 10.53 THz to 4.4879 THz.
Conclusion
- Summary
- Suggestions for Further Work
We calculated various performances of the simulated device in the sub-threshold region such as off-current, on-off current ratio, inverse sub-threshold slope, etc. It is found that both the on-off current ratio and the inverse sub-threshold slope are improved with underlap. It is observed that with the increase of underlap, the height of the channel barrier increases and therefore significantly suppresses the off-state current.
Increasing underlap length also results in reduction of on-state current, but this reduction is not as significant as the reduction of off-state current. We also investigated the performance measures of the device such as transconductance, intrinsic gate delay and intrinsic cutoff frequency with underlap and also with gate bias. We also investigated the gate capacitance and contribution of its various components with underlap and also with gate bias.
The result shows that approximately 50 percent of the gate capacitance comes from the edge field capacitance. The gate capacitance of the device decreases with underlap, so it is expected that the intrinsic gate delay will decrease and the cutoff frequency will improve with underlap. But the transconductance and current also decrease with overlap and dominate the capacitance reduction, resulting in an intrinsic increase.
But the transconductance and current of the device increases drastically with gate bias and dominates over the increase in gate capacitance, hence there is a decrease in the internal gate delay and increase in the internal cutoff frequency with underlap. With a very small modification, this model can be used to simulate the Schottky switch silicon nanowire transistor. With a very small change in our entity description file, our model can handle these kinds of new structures.
In that case, one must take an atomistic approach to Hamiltonian formulaism, but the 3D Poison equation developed herein can still be used without any noticeable change.
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Appendix B
