Assembly issues in three flip chip processes
Zhaowei Zhong
Nanyang Technological University, Singapore
Introduction
Flip chip interconnection is the smallest and thinnest IC (integrated circuit) assembly on board and in package. The short interconnection between flip chip and substrate also improves electrical performance. Industry applications in which flip chip technology is used include automotive, computers, smart cards, telecommunication equipment, LCDs (liquid crystal displays) and watch modules, etc. Besides the C4 (controlled collapse chip connection) process invented over 30 years ago, many simpler, lower cost and lower-temperature processes for flip chip assemblies have been developed (Lau, 1995; Zhonget al., 1997; Zhong and Goh, 1999; Kloeseret al., 1997). In other words, nowadays electronics packaging engineers have many more choices to select a flip chip assembly process for a particular application than they used to do. When a flip chip assembly process is selected, both reliability and cost should be taken into account. A simple process, low cost and reasonable reliability (not necessarily the best reliability) may be the key reasons for the decision made eventually (Zhong, 1999).
In this paper, three simple and low-cost flip chip assembly processes are discussed. First, flip chip on board using non-conductive adhesive is evaluated. This process can give reasonable reliability and high assembly yield, when the parameters for epoxy placement and bonding are optimised. Second, the flip chip assembly process using reflowable no-flow underfill is discussed. Because the underfill epoxy is already placed in the gap between the IC chip and the substrate before reflow, it is not easy to control the solder joints' collapse and obtain the desired solder-joint shapes and stand-off distance during reflow. Finally, the stud bump bonding process is also discussed. It is not easy although possible to maintain the optimal dipping of the conductive adhesive, when the average height of the gold bumps is small. Some solutions for overcoming the above-mentioned difficulties are presented in this paper.
Flip chip attachment using
non-conductive adhesive
A typical flip chip attachment using non-conductive adhesive is very simple, and involves only two process steps:
1 non-conductive adhesive placement; 2 IC placement and bonding;
as shown in Figure 1. This process is a solderless flip chip mounting method, and can give reasonable reliability and high assembly yield at low cost, when the parameters for epoxy placement (dispensing volume and pattern, shelf life
of the epoxy) and bonding conditions (bonding force, temperature and time, cooling temperature) are optimised by performing design of experiments (DOE).
In this study, an L18orthogonal array (Ross, 1988) was
selected for the DOE. Seven parameters (dispensing volume and pattern, shelf life of the epoxy, bonding force, temperature and time, cooling temperature) with three levels and one parameter (surface cleanliness) with two levels were investigated in the experiments. Eighteen experiments with four runs for each experiment were conducted, and the in-circuit voltage and functional tests were performed after the bonding experiments.
The analysis of variance (ANOVA) technique was used to establish the relative significance of the individual parameters. The ANOVA analysis revealed with 99 per cent confidence that dispensing volume and pattern of the non-conductive epoxy, and bonding force and temperature were the important parameters significantly affecting the assembly yield.
Based on the DOE results, the settings for five parameters were determined. However, the other three parameters needed further investigation. Therefore, another DOE was carried out. After the two DOE analyses, the settings for all the eight parameters were determined. Confirmation and yield testing experiments were then conducted. The assembly yield was found to be over 97 per cent. Failure analysis helped to improve the assembly yield even more. Reliability tests were also carried out and satisfactory results were obtained.
Flip chip assembly using reflowable
no-flow underfill
The flip chip assembly process using reflowable no-flow underfill was invented to dispense the reflowable no-flow underfill epoxy on a substrate and then perform the solder bump reflow and underfill epoxy curing simultaneously. The aim of the effort was to reduce the cycle time and cost, and to improve the production efficiency. However, this process was not widely used in production mainly because of the lack of successful reflowable no-flow underfill epoxies. Therefore, special reflowable and no-flow underfill materials were developed (Gamotaet al., 1997; Wonget al., 1997).
The process using reflowable no-flow underfill for eutectic solder flip chip assemblies is shown in Figure 2. The process steps are:
1 epoxy placement;
2 fluxing on the solder bumps or the pads; 3 IC placement; and
4 reflow.
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Microelectronics International 17/2 [2000] 15±18
#MCB University Press [ISSN 1356-5362]
Keywords
Flip chip, Adhesives, Underfill, Bonding, Stud bump bonding
Abstract
As a comparison, the typical assembly steps for eutectic solder flip chip assemblies using normal underfill epoxy (as shown in Figure 3) are:
1 fluxing; 2 IC placement; 3 reflow; 4 underfilling; and 5 curing of underfill epoxy.
The process using no-flow underfill does not involve the process steps of underfilling and curing of the underfill epoxy.
In order to obtain high assembly yield, the last process step must be well controlled. A normal reflow profile may not work. Because the underfill epoxy is already placed in the gap between the IC chip and the substrate before reflow, it is not easy to control the solder joints' collapse and obtain the desired solder-joint shapes and stand-off distance during reflow.
One solution to solve the assembly problem is to do bonding similar to that in the assembly process using non-conductive adhesive. After IC chip placement, a suitable force and temperature profile are applied. In the assembly process using non-conductive adhesive, relatively large bonding force can be applied because gold bumps are used. However, in the process using no-flow underfill, the bonding force must be small and optimised. Too much bonding force produces completely collapsed solder joints and even causes bridging of solder bumps and/or pads which results in short circuit interconnections.
SBB process
SBB (stud bump bonding) process was introduced as another solderless flip chip mounting method for low-cost
and high-density mounting of bare chips on glass epoxy or glass polyimide resin printed circuit boards. It was claimed that the process was inexpensive and reliable, and was reworkable before curing of the underfill epoxy (Lau, 1995).
The typical SBB process flow is shown in Figure 4. The assembly steps are:
1 levelling of stud bumps; 2 dipping of conductive adhesive; 3 IC placement;
4 curing of conductive adhesive; 5 underfilling; and
6 curing of underfill epoxy;
followed by the optional steps: 7 encapsulation; and 8 curing of encapsulant.
SBB process was also investigated in this study. The gold pull-off bumps were formed with a gold wire-bonding machine. Then the bumps were levelled by applying force with a flip chip bonder. The levelling force used to deform the bumps had to be optimised to form a proper bump shape. Higher levelling force produced thinner and flatter bumps with increasing shear strength. As the example of an application, when 0.89 N levelling force per bump was used, the average diameter and height of the deformed bumps were about 75m and 28m respectively, and the
average of the bump shear strength was 66 grams per bump. Dipping of conductive adhesive is very important in order to have good electrical interconnections between the gold bumps of the flip chip and the gold pads of the substrate. Too little conductive adhesive tends to produce open interconnections, while too much conductive adhesive results in bridging of gold bumps and/or pads, which produces short circuit interconnections.
The volume of conductive adhesive was controlled by maintaining the optimal depth of the conductive adhesive pool (bath) placed on a rotating disk. Too small and too large depths of the pool resulted in too little and too much conductive adhesive dipped, respectively. It was not easy although possible to maintain the optimal depth of the conductive adhesive pool within a very small tolerance, when the average height of the gold bumps was small. Increasing the height of the bumps would make it much easier to maintain the depth of the conductive adhesive pool within a larger tolerance.
As a feasibility study, double bumping was tried, which increased the heights of the bumps and made the control of dipping much easier. This also increased the stand-off distance and the volume of underfill materials. The gold bumps obtained by single bumping and double bumping before and after levelling with different levelling forces are shown in Figures 5, 6 and 7.
Figure 1
Process flow of the flip chip assembly using non-conductive adhesive
Figure 2
The procedure of the flip chip assembly process using reflowable no-flow underfill
Figure 3
The procedure of the flip chip assembly process with eutectic solder and underfill
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Zhaowei Zhong
Assembly issues in three flip chip processes
Figure 4
The typical SBB process flow
Figure 5
Gold bumps produced by (a) single bumping and (b) double bumping, before levelling
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Zhaowei Zhong
Assembly issues in three flip chip processes
Conclusion
Three simple and low-cost flip chip assembly processes were evaluated. Flip chip on board using non-conductive adhesive could give reasonable reliability and high assembly yield, when the parameters for epoxy placement and bonding were optimised. The process using reflowable no-flow underfill involved fewer process steps compared to the typical eutectic solder flip chip assembly process. Strict process control to apply a suitable force and temperature profile during bonding was tried in order to obtain high assembly yield. As for the stud bump bonding process, it was not easy although possible to maintain the optimal dipping of the conductive adhesive, when the average height of the gold bumps was small. As a feasibility study, double bumping was tried, which increased the heights of the bumps and made the control of dipping much easier.
References
Gamota, D.R. and Melton, C.M. (1997), ``Advanced flip chip materials: reflowable underfill systems'',Advances in Electronic Packaging, EEP-Vol. 19-1, pp. 365-71.
Kloeser, J., Kutzner, K. and Gross, K. (1997), ``A new production line for low cost flip chip assembly'',Proceedings of the Technical Program, Surface Mount International, USA, pp. 257-66.
Lau, J.H. (1995),Flip Chip Technologies, McGraw-Hill, New York, NY.
Ross, P.J. (1988),Taguchi Techniques for Quality Engineering, McGraw-Hill Book Company, New York, NY.
Wong, C.P., Shi, S.H. and Jefferson, G. (1997), ``High performance no flow underfills for low-cost flip-chip applications'', Proceedings of 1997 Electronic Components and Technology Conference, pp. 850-8.
Zhong, Z.W. (1999), ``Assembly and reliability of flip chip on boards using ACAs or eutectic solder with underfill'', Microelectronics International, Journal of The
Microelectronics and Packaging Society ± Europe, Vol. 16 No. 3, pp. 6-14.
Zhong, Z.W. and Goh, K.S. (1999), ``Assembly and reliability of flip chip on various substrate materials'',Proceedings of 1st International Workshop on Electronics Materials and Packaging (EMAP '99), Singapore, pp. 12-20.
Zhong, Z.W., Wong, S. and Nishikawa, T. (1997), ``A study of flip chip on board mounting process using anisotropic conductive films'',Proceedings of SEMICON Test, Assembly and Packaging 97, Singapore, pp. 157-64.
Figure 6
Gold bumps produced by (a) single bumping and (b) double bumping, after levelling with levelling force 0.22 N per bump
Figure 7
Gold bumps produced by (a) single bumping and (b) double bumping, after levelling with levelling force 0.67 N per bump
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Assembly issues in three flip chip processes
