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Implementation of Ultra Low Power Diode load based Gilbert cell Mixer for Wireless Applications
Priyanka1, Alok Kumar Singh2, Neeta Pandey3
1, 2, 3 Department of Electronics and Communication Delhi Technological University
Delhi, INDIA
1[email protected], 2[email protected], 3[email protected]
Abstract—An Ultra Low Power Diode (ULPD) load based down conversion mixer is presented in this paper. The mixer is designed to operate at 2.5 GHz RF frequency with 250MHz Intermediate frequency. The conversion gain provided by the mixer is maximum ~8dB at 2.1GHz RF frequency. The power consumption for the mixer core circuit is ~17mW. The mixer presents good RF to IF port isolation with input return loss less than zero. The Input Third Order Intercept increases from
~9dBm to 15.8 dBm for variation of the source degeneration inductors from 1 nH to 20 nH. The IIP3 is 11.64dBm at 4 GHz RF frequency with 1nH inductor. The mixer is simulated with 1.8V voltage supply using 180nm CMOS process. The RF power is -30dBm and LO power is set to 5dBm.
Keywords— Conversion gain, linearity, down conversion, Gilbert Mixer, Ultra low power diode.
I. INTRODUCTION
The enormous growth in demand for handheld and wireless communication devices like cell phones, personal digital assistants (PDAs) has motivated researchers to develop RF circuits with enhanced performance on silicon IC. Although for radio frequency applications, integrated circuits realized by Bipolar and Gallium Arsenide technologies usually exhibit high performance, CMOS process is so exquisite because it substantially scales down the cost and complexity by implementing both analog and digital blocks of communication ICs. The advancement in CMOS technology has enabled the designing of integrated transceivers fulfilling all the consumer and commercial demands of portability, extended battery life (low power consumption due to minimized external components), high data rate and economical solutions for wireless communication.
A mixer is the fundamental building block of CMOS receiver, which performs the task of frequency translation to a higher or lower spectrum for making the task of signal processing, easier and inexpensive. The designing and optimization of mixer requires a compromise between conversion gain, noise figure, port-to-port isolation, linearity, voltage scaling and power consumption.
Fundamentally, mixers can be classified into active and passive with respect to their dc power consumption. Active mixers are capable of providing conversion gain that reduces noise contributed by the subsequent stages of the receiver. This conversion gain lowers the LO power required for their operation so they are widely used in RF applications. Passive mixers, on the other hand can operate at very high frequency (>10GHz) but always exhibit conversion loss rather than gain.
In addition to excellent IM performance, they offer high linearity and fast switching but at the expense of LO power required. Passive mixers are therefore popular in microwave and base station circuits [14]. However, Large LO drive along with good LO-to-RF and LO-to-IF isolation is difficult to realize in low voltage and low power environments, therefore Active CMOS mixers are preferred to their passive counterpart in designing integrated circuitry. Various topologies of active mixer such as Single FET [15], Dual gate and Gilbert mixer (single and double balanced) [16] have been reported so far.
Out of the various mixer topologies available, Gilbert cell topology has been extensively adopted for high performance IC applications. As compared to Single balanced topology, Double balanced mixer offers salient characteristics of higher linearity, port to port isolation, improved suppression of spurious gain products (symmetry leads to the suppression of even order products of LO / RF).
In order to achieve these enhanced features at low voltage, several configurations have been proposed for the Double Balanced Gilbert mixer e.g. Current bleeding and Folded configuration. Using current bleeding approach, gm of the RF trans-conductance stage can be preserved while raising the value of load. However, this topology enhances conversion gain without affecting the power consumption, leakage currents also get introduced into the mixer circuit. These leakage currents are attributed by the parasitic capacitances of bleeding transistors. Parasitic capacitances not only constraints the bandwidth but also deteriorates the conversion gain by creating alternate path of signal leakage to the substrate ground. A folded cascode mixer structure can overcome the problem of voltage headroom of Gilbert mixer by eliminating stacked configuration of the transconductance and the switching stage
IEEE INDICON 2015 1570172271
but current consumption of this configurat times to that in the conventional Gilbert cell [ In this paper, a new type of active load fo mixer is presented, which occupies consid than the passive load while maintaining low and power consumption.
Fig.1. Basic Double Balanced Gilbert Mi
II. VARIOUS LOADS FOR MIX Different types of loads have been r designs e.g. passive resistor, simple PMO PMOS loads with certain other passive/acti gate or forming a negative feedback path mirror, inductive load and RLC tuned load[3
In CMOS technology, resistors with s value and reasonable physical size are dif therefore, they are not preferred in modern d load is replaced by an active load (i.e., lo MOSFETs), it can significantly reduce the r as well as can yield higher gain for a m conversion gain with active load is achieved small signal resistance [12].
An active load can be implemented using MOS (i.e. gate of MOS transistor is connect transistor). This configuration when used tends to achieve larger bandwidths but has lo it has relatively lower value of output im alternative load, Current mirror can provide to high output impedance) but at the expe [12]. When passive elements with PMOS enhancing gain or linearity, the power cons
tion becomes two [2].
or a CMOS Gilbert derably lesser area wer leakage current
ixer cell
XER
reported in mixer OS transistor[2] , ive elements at its h[17][18], current
].
strictly controlled fficult to fabricate designs. If passive oad realized using required chip area mixer. The higher
d due to its higher
g diode connected ted to the drain of as load generally ower gain because mpedance. As an e higher gain (due ense of bandwidth load are used for sumption and area
of the circuit increases again load. Inductive and tuned lo around a centre frequency so operation. Among the variou observed that a PMOS load b better performance in terms requirements. However, for se desired performance either an extra circuitry is needed.
In view of the different lo mixer, a new type of Active l power diode) is presented here and linearity but also consumes
A. Ultra Low Power Diode Two configurations of diode shown in the figure below. F MOS diode with its gate and diode is reverse-biased, the so connected to the gate. The lea characterized by the drain curre and +Vbs= -VD (where -ve sig the diode when biased in reve current causes considerable inc the circuit. Although, increas reduce the leakage current bu poor forward drive capability.
ULPD shown in fig.2(b) NMOS and PMOS transisto transistor is connected to the vice versa. When compared t diode has capability of reducin while maintaining the similar fo
Fig.2 (a) Standard MOS Diode When ULPD is in forward m forward biased standard connected in series and ther comparable to that of a stan mode[1]. As source terminal o be connected together as well voltages, their leakage current or weak inversion regions, thresholds. An important feat
as in case of passive resistive ads are suitable for operation cannot be used for wideband us available loads, it has been iased in the linear region gives s of gain, linearity and area etting a proper gate bias to get n additional control voltage or
ads used in the used in Gilbert load called as ULPD (ultra low which not only provides higher s less power.
using MOSFET transistors are Figure 2(a) shows the standard drain at same potential. If this ource of the MOS appears to be akage current that flows is thus ent under the condition vgs = 0V gn shows the voltage applied to erse direction) [1]. This leakage crease in power consumption of se in Vth of the transistor can ut will consequently lead to its
consists of a combination of rs, in which gate of NMOS source of PMOS transistor and to standard MOS diodes, ULP ng the leakage current strongly forward current drive.
e (b) Ultra low power diode mode, it can be regarded as two
NMOSFET and PMOSFET refore it has forward current ndard diode in reverse biased of NMOS and PMOS appears to
l as both operate with negative is small. It operates in moderate
depending upon the device ture of ULPD is its ability to
serve as a resistor by operating the transis region [4-6].
The equivalent impedance of ULPD at hig small input signal is given as-
( ) s As R Bs sX C
Z + +
=
2+
As observed in above expression, the imped load is a second order function with two pole Where R and X denotes the real and imag zero of the impedance function respectively are the positive coefficients, which can be ex
2
1 o
o
r
r R = +
(
Cgd1 Cgd2) (
ro1 ro2)
X = + +
(
Cgd1 Cgd2)(
Cgs1 Cgs2 Cgd2) (
roA= + + +
( ) ( ) (
(
2 2)
1 2
2 1 2
1 2 1
1
1
o m o
gd
o gd o
o gs gs
r g r C
r C r r C C B
+ +
+ +
+ +
=
2 2 1
1 g
m1r
og
mr
oC = + +
Here ro1 and ro2 are drain source output res
2
g
m are transconductances, Cgs1 and Cgs2capacitances and Cgd1 and Cgd2 are the gate-d of the NMOS and PMOS respectively. Th introduced by the load enhances the bandwid As observed in [1] the leakage current re in ULPD, which for a MOS diode exists in na at zero VGS and dominates with back gate mode.
ULPD finds applications in level keep circuits, charge pumps [13], memory cells [1 paper, it has been employed as load in Gilber
III. ULPDLOADBASEDMIX Fig. 3 shows the proposed Gilbert mixer Gilbert mixer primarily encompasses Transconductance stage composed of trans functioning as the voltage to current conver signal, which is to be down-converted, is transistors and hence two currents +IRF and for proper operation it should be ensured tha not be steered into the saturation region [4]
incorporates transistors M1 to M4 multiplyi current to the LO signal applied. Load st comprising transistors (M10, M12) and (M9, two loads for the mixer. The linearity can adding degeneration resistors R1 and R2
devices which are used for unbalanced to b
stors in the linear
gh frequencies for
ance of the ULPD es and a zero.
ginary parts of the y and A, B and C xpressed as:
)
2
1 o
o r
r +
)
1 1 o m
r + g
sistances,
g
m1and are gate source drain capacitances he additional zero dth of the mixer.emarkably reduces ano-amperes range e effect in reverse
pers in MTCMOS 1] etc. Here in this rt Mixer.
XER
r with ULPD load.
s three stages.
istors M5 and M6
rsion unit. The RF s applied to these
–IRF are produced at M and M might ]. Switching stage ing the RF signal tage uses ULPDs M11) forming the n be enhanced by . Baluns are the balanced (or single
ended to differential) transform well as for balanced to unbal output terminals.
Fig.3 Proposed Gilbert
IV. SIMULATI The proposed down conver using BSIM3 0.18µm RF C operated with a 1.8V supply v 6mA.
Fig.4 shows the variation o frequency. The positive conv 100MHz to 6 GHz with maxim power consumption for the mi GHz operating frequency. The dBm for simulation.
Fig.4 Conversion gain (dB) versus
mation at RF and LO inputs as lanced transformation at the IF
t Mixer with ULPD load
IONRESULTS
rsion Gilbert mixer is simulated CMOS process. The mixer is voltage with an active current of
of conversion gain with RF version gain is obtained from mum value ~8dB at 2.1GHz. The
ixer core circuit ~17mW at 2.5 e RF Input power is set to -30
RF frequency (Hz) with ULPD load
Fig.5 Input IP3 (dBm) versus RF frequen
Fig.6 Conversion gain (dB) versus RF Pow In Fig.5, the variation of IIP3 with RF fre The mixer achieves the input third order as11.64 dB at 4GHz frequency and 4.85 Output IP3 has maximum value ~17.34 Fig.6, conversion gain is approximately 20dBm with maximum value 7.8dB and then
Fig.7 Conversion gain (dB) versus LO P ncy (Hz)
wer (dBm)
equency is shown.
intercept as high dB at 100 MHz at 3.4GHz. From constant up to - n decreases.
Power (dBm)
Fig.8 S11 (dB) versu
Fig.9 S12 (dB) versu The LO power required for get is shown in fig.7. Fig.8 and f RF port return loss and RF-IF frequency. S11 obtained is less -450 dB for the entire frequ linearity of the mixer is en degeneration inductors in the t depicts the variation of conver the value of these inductors. It mixer increases and the corre increase the value of inductor tradeoffs involved between linearity. However, there is a increased for linearity enhancem
TABLE I. MIXER PARAMETERS VALUES (AT 2.5 GH
Ls(nH) Conversion Gain (dB)
1 7.782 5 6.591 10 4.217 15 2.005 20 0.171
us RF frequency (Hz)
us RF frequency (Hz)
tting a specified conversion gain fig.9 shows the simulated Input F port isolation as a function of s than 0db and S22 is less than
uency range of operation. The nhanced by using the source transconductance stage. Table I rsion gain, IIP3 and OIP3 with is observed that linearity of the sponding gain decreases as we r 1nH to 15nH because of the the Conversion gain and the a limit up to which Ls can be
ment.
S FOR DIFFERENT INDUCTOR (LS) HZ RF FREQUENCY)
Input Intercept Point (dBm)
Output Intercept Point (dBm)
8.996 16.778 11.490 18.081 12.854 17.071 14.319 16.324 15.807 15.978
TABLE II: PERFORMANCE COMPARISON WITH OTHER REPORTED PAPERS
References
Parameters
This
work [7] [8] [9] [10] [11]
CMOS Technology
(µm)
0.18 0.18 0.13 0.18 0.18 0.18
CG (dB) 7.97 7.5-
10.8 3-8 11 15.7 5.9
RF freq (GHz) 0.5-6 3.1-
8.1 1-10 0.3-25 2.4 1-1.6 Core Mixer
Power (mW) 17 8 8.4 71 8.1 20.7
S11 (dB) < 0 < -12 - < -5 - - IIP3 (dBm) 4.9-
11.6 -3.4 -7 -4 - 1 4.1
VDD (V) 1.8 1.5 1.2 - 3 1.8
V. CONCLUSION
The ULPD load presented here, reduces the leakage power and hence the power consumption for the Mixer. By operating the diode in the linear region, Gilbert mixer with reasonably high linearity and adequately large conversion gain can be designed. Besides this, ULPD enhances the bandwidth of the mixer also. The comparison of proposed mixer with other implemented mixers is shown in Table II. However, this mixer has a voltage headroom limitation but by utilizing emerging multi-Vth (Threshold voltage) fully SOI (Silicon on Insulator) CMOS process, sufficiently low voltage operation can be achieved [1].
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