4.3 Legacy GPS Signals
4.3.1 Frequencies and Modulation Format
provide additional design parameters for waveform designers to use. The resulting modulation designs can provide enhanced performance when bandwidth is limited (due to implementation constraints at transmitter and receiver, or due to spectrum allocations). Also, modulations can be designed to better share limited frequency bands available for use by multiple GNSS. The spectra can be shaped in order to limit interference and otherwise spectrally separate different signals. In order to obtain adequate performance, such modulation design activities must carefully con- sider a variety of signal characteristics in the time and frequency domains, and they should not concentrate exclusively on spectrum shape.
activated, the P code is encrypted to form what is known as the Y-code. The Y-code has the same chipping rate as the P code. Thus, the acronym often used for the preci- sion (encrypted) code is P(Y) code.
Since the PPS (primarily military) users have access to the cryptographic keys and algorithms used in the AS process but the SPS (primarily civil) users do not, then AS denies access to the P code by SPS users. In the past, both the C/A code and the P(Y) code, as well as the L1 and L2 carrier frequencies, were subjected to an encrypted time-varying frequency offset (referred to as dither) plus an encrypted ephemeris and almanac offset error (referred to asepsilon) known as SA. SA denied the full accuracy of GPS to the stand-alone SPS users. However, SA has been deacti- vated on all GPS satellites since May 1, 2000, so this subject will not be further discussed in this chapter.
Note in Figure 4.5 that the same 50-bps navigation message data is combined with both the C/A code and the P(Y) code prior to modulation with the L1 carrier.
An exclusive-or logic gate is used for this modulation process, denoted by⊕. Since the C/A code⊕data and P(Y) code⊕data are both synchronous operations, the bit transition rate cannot exceed the chipping rate of the PRN codes. Also note that BPSK modulation is used with the carrier signals. The P(Y) code⊕data is modulated in phase quadrature with the C/A code⊕data on L1. As shown in Figure 4.5, the L1 carrier is phase shifted 90º before being BPSK modulated by the C/A code⊕data.
Then this result is combined with the attenuated output of the BPSK modulation of L1 by the P(Y) code⊕data. The 3-dB amplitude difference and phase relationship between P code and C/A code on L1 are illustrated by the vector phase diagram in Figure 4.6. Figure 4.7 illustrates the result of P code⊕ data and C/A⊕data. As observed in Figure 4.7, the exclusive-or process is equivalent to binary multiplica-
P(Y) code
Other information
P(Y) code⊕data
C/A code⊕data 154f0carrier
120 f carrier0
×120
×154
+10
+20
BPSK modulator
BPSK modulator
BPSK modulator P(Y) code
generator f0clock
C/A code generator
Data generator
Switch
−3 dB
50-bps data 1,000 Hz
50 Hz
L2 signal 1,227.6 MHz
L1 signal 1,575.42 MHz
Handover information
Σ
90°
X1 epoch
X1 epoch
−6 dB P(Y) code data or P(Y) code or C/A code data
⊕
⊕
X1 epoch Limiter
f0/10 clock
f0= 10.22999999543 MHz
Figure 4.5 Legacy GPS satellite signal structure.
2A
1,575.42 MHz = carrier frequency 1.023 Mbps = clock rate
50 bps = data rate C/A code phase
A 90°
1,575.42 = carrier frequency 10.23 Mbps = clock rate 50 bps = data rate P code phase
P(Y) code signal = long secure code with 50-bps data C/A code signal = 1023 chip Gold code with 50-bps data
Li(ω1t A P t)= [ ( )i ⊕D ti( )]cos(ω1t)+ 2 [A G ti( )⊕D ti( )]sin(ω1t) Figure 4.6 GPS signal structure for L1.
1 0 1 0 0 1 0 0 1 0 0 0
0 1
1 0
50-Hz data P(Y) code
0 1
50-Hz data
1 0 1 0 1 1 0 1 1 0 1 1 1
1 0 1
P(Y) code⊕data
C/A code
C/A code⊕data 0
Figure 4.7 GPS code mixing with data.
tion of two 1-bit values yielding a 1-bit product using the convention that logical 0 is plus and logical 1 is minus. There are 204,600 P(Y) code epochs between data epochs and 20,460 C/A code epochs between data epochs, so the number of times that the phase could change in the PRN code sequences due to data modulation is relatively infrequent, but the spectrum changes due to this modulation are very significant.
Figure 4.8 illustrates how the signal waveforms would appear before and after the BPSK modulation of one P(Y) code⊕data transition and one C/A code⊕data transition. There are 154 carrier cycles per P(Y) code chip and 1,540 carrier cycles per C/A code chip on L1, so the phase shifts on the L1 carrier are relatively infre- quent. The L2 frequency (1,227.60 MHz) can be modulated by either the P(Y) code
⊕data or the C/A code⊕data or by the P(Y) code alone as selected by the CS. The P(Y) code and C/A codes are never present simultaneously on L2 prior to GPS mod- ernization (see Section 4.5), unlike the case with L1. In general, the P(Y) code⊕data is the one selected by the CS. There are 120 carrier cycles per P(Y) code chip on L2, so the phase transitions on the L2 carrier are relatively infrequent. Table 4.2 summa- rizes the GPS signal structure on L1 and L2.
The PPS user has the algorithms, the special Y-code hardware per channel, and the key to gain access to the Y-code. PPS receivers formerly included a precise posi- tioning service security module (PPSSM) to store and process the cryptographic keys and an auxiliary output chip (AOC) to produce the Y-code. Current generation PPS receivers are built around a security architecture referred to as the selective availabil-
(a)
(b)
(c)
(d)
(e)
(f)
(g)
0 180 360 540 720 900 1080
Phase (degrees)
Figure 4.8 GPS L1 carrier modulation: (a) L1 carrier (0º phase), (b) L1 carrier (90º phase), (c) P(Y) code⊕data, (d) C/A code⊕data, (e) P(Y) code⊕data BPSK modulated on L1 carrier (0º phase) with 3-dB attenuation, (f) C/A code⊕data BPSK modulated on L1 carrier (90º phase), and (g) composite modulated L1 carrier signal.
ity/antispoofing module (SAASM). The use of the AS Y-code denies direct (SPS GPS receiver) access to the precision code. This significantly reduces the possibility of an enemy spoofing a PPS receiver (i.e., transmitting a stronger, false precise code that captures and misleads the receiver). However, AS also denies direct access to the precision code to all SPS users, friendly or otherwise. Indirect access is still possible as discussed in [11] and Section 5.14.
4.3.1.1 Direct Sequence PRN Code Generation
Figure 4.9 depicts a high-level block diagram of the direct sequence PRN code gen- eration used for GPS C/A code and P code generation to implement the CDMA tech- nique. Each synthesized PRN code is derived from two other code generators. In each case, the second code generator output is delayed with respect to the first before their outputs are combined by an exclusive-or circuit. The amount of delay is different for each SV. In the case of P code, the integer delay in P-chips is identical to the PRN number. For C/A code, the delay is unique to each SV, so there is only a table lookup relationship to the PRN number. These delays are summarized in Table 4.3. The C/A code delay can be implemented by a simple but equivalent tech- nique that eliminates the need for a delay register. This technique is explained in the following paragraphs.
The GPS C/A code is a Gold code [12] with a sequence length of 1,023 bits (chips). Since the chipping rate of the C/A code is 1.023 MHz, the repetition period of the pseudorandom sequence is 1,023/(1.023×106Hz) or 1 ms. Figure 4.10 illus- trates the design architecture of the GPS C/A code generator. Not included in this diagram are the controls necessary to set or read the phase states of the registers or the counters. There are two 10-bit shift registers, G1 and G2, which generate maxi- mum length PRN codes with a length of 210−1=1,023 bits. (The only state not used is the all-zero state). It is common to describe the design of linear code generators by means of polynomials of the form 1+ ΣXi, whereXimeans that the output of theith cell of the shift register is used as the input to the modulo-2 adder (exclusive-or), and the 1 means that the output of the adder is fed to the first cell [8]. The design specifi- cation for C/A code calls for the feedback taps of the G1 shift register to be con- nected to stages 3 and 10. These register states are combined with each other by an exclusive-or circuit and fed back to stage 1. The polynomial that describes this shift register architecture is: G1=1 X3 X10. The polynomials and initial states for both
Table 4.2 Legacy GPS Signal Structure
Signal Priority Primary Secondary
Signal designation L1 L2
Carrier frequency (MHz) 1,575.42 1,227.60 PRN codes (Mchip/s) P(Y)=10.23 and
C/A=1.023
P(Y)=10.23 or C/A=1.023 (Note 1) Navigation message data
modulation (bps) 50 50 (Note 2)
1. The code usually selected by the CS on L2 is P(Y) code.
2. The 50-Hz navigation data message is usually modulated on L2 P(Y) code but can be turned off by the CS. There are three possibilities on L2: P(Y) code with data, P(Y) code with no data, and C/A code with data.
the C/A-code and P-code generator shift registers are summarized in Table 4.4. The unique C/A code for each SV is the result of the exclusive-or of the G1 direct output sequence and a delayed version of the G2 direct output sequence. The equivalent delay effect in the G2 PRN code is obtained by the exclusive-or of the selected posi- tions of the two taps whose output is called G21. This is because a maximum-length PRN code sequence has the property that adding a phase-shifted version of itself produces the same sequence but at a different phase. The function of the two taps on the G2 shift register in Figure 4.10 is to shift the code phase in G2 with respect to the code phase in G1 without the need for an additional shift register to perform this delay. Each C/A code PRN number is associated with the two tap positions on G2.
Table 4.3 describes these tap combinations for all defined GPS PRN numbers and specifies the equivalent direct sequence delay in C/A code chips. The first 32 of these PRN numbers are reserved for the space segment. Five additional PRN numbers, PRN 33 to PRN 37, are reserved for other uses, such as ground transmitters (also referred to as pseudosatellites orpseudolites). Pseudolites were used during Phase I (concept demonstration phase) of GPS to validate the operation and accuracy of the system before any satellites were launched and in combination with the earliest sat- ellites. C/A codes 34 and 37 are identical.
The GPS P code is a PRN sequence generated using four 12-bit shift registers designated X1A, X1B, X2A, and X2B. A detailed block diagram of this shift register architecture is shown in Figure 4.11 [10]. Not included in this diagram are the con- trols necessary to set or read the phase states of the registers and counters. Note that
G1 Generator
G2 Generator
X1 generator
X2 generator
X1 epoch G1(t)
G2(t)
÷10
Clock 10.23 MHz
10.23 MHz
X1 epoch Delay di Tg
Delay i Tp Satellite i
Satellite i X1(t)
X2(t) 1.023 MHz
1.023 Mchip/s rate
1,023 chip period = 1 ms period
10.23 Mchips/s rate
15,345,000 chip period = 1.5 sec period X1 epoch
C/A code
Gi(t) = G1(t)⊕G2(t + di Tg)
P Code
Pi(t) = X1(t)⊕X2(t + i Tp)
10.23 Mchips/s rate 15,345,037 chip period 37 chips longer than X1(t) .
Figure 4.9 GPS code generators.
Table 4.3 Code Phase Assignments and Initial Code Sequences for C/A Code and P Code SV PRN
Number
C/A Code Tap Selection
C/A Code Delay (Chips)
P Code Delay (Chips)
First 10 C/A Chips (Octal)1
First 12 P Chips (Octal)
1 2⊕6 5 1 1440 4444
2 3⊕7 6 2 1620 4000
3 4⊕8 7 3 1710 4222
4 5⊕9 8 4 1744 4333
5 1⊕9 17 5 1133 4377
6 2⊕6 18 6 1455 4355
7 1⊕8 139 7 1131 4344
8 2⊕9 140 8 1454 4340
9 3⊕10 141 9 1626 4342
10 2⊕3 251 10 1504 4343
11 3⊕4 252 11 1642 4343
12 5⊕6 254 12 1750 4343
13 6⊕7 255 13 1764 4343
14 7⊕8 256 14 1772 4343
15 8⊕9 257 15 1775 4343
16 9⊕10 258 16 1776 4343
17 1⊕4 469 17 1156 4343
18 2⊕5 470 18 1467 4343
19 3⊕6 471 19 1633 4343
20 4⊕7 472 20 1715 4343
21 5⊕8 473 21 1746 4343
22 6⊕9 474 22 1763 4343
23 1⊕3 509 23 1063 4343
24 4⊕6 512 24 1706 4343
25 5⊕7 513 25 1743 4343
26 6⊕8 514 26 1761 4343
27 7⊕9 515 27 1770 4343
28 8⊕10 516 28 1774 4343
29 1⊕6 859 29 1127 4343
30 2⊕7 860 30 1453 4343
31 3⊕8 861 31 1625 4343
32 4⊕9 862 32 1712 4343
332 5⊕10 863 33 1745 4343
342 4⊕103 9503 34 17133 4343
352 1⊕7 947 35 1134 4343
362 2⊕8 948 36 1456 4343
372 4⊕103 9503 37 17133 4343
1. In the octal notation for the first 10 chips of the C/A code, as shown in this column, the first digit (1) represents a 1 for the first chip and the last three digits are the conventional octal representation of the remaining 9 chips. For example, the first 10 chips of the SV PRN number 1 C/A code are 1100100000.
2. PRN codes 33 through 37 are reserved for other uses (e.g., pseudolites).
3. C/A codes 34 and 37 are identical.
the X1A register output is combined by an exclusive-or circuit with the X1B register output to form the X1 code generator and that the X2A register output is combined by an exclusive-or circuit with the X2B register output to form the X2 code genera- tor. The composite X2 result is fed to a shift register delay of the SV PRN number in chips and then combined by an exclusive-or circuit with the X1 composite result to generate the P code.
The design specification for the P code calls for each of the four shift registers to have a set of feedback taps that are combined by an exclusive-or circuit with each other and fed back to their respective input stages. The polynomials that describe the architecture of these feedback shift registers are shown in Table 4.4, and the logic diagram is shown in detail in Figure 4.11.
Referring to Figure 4.11, note that the natural cycles of all four feedback shift registers are truncated. For example, X1A and X2A are both reset after 4,092 chips, eliminating the last three chips of their natural 4,095 chip sequences. The registers X1B and X2B are both reset after 4,093 chips, eliminating the last two chips of their natural 4,095 chip sequences. This results in the phase of the X1B sequence lagging by one chip with respect to the X1A sequence for each X1A register cycle. As a result, there is a relative phase precession between the X1A and X1B registers. A similar phase precession takes place between X2A and X2B. At the beginning of the GPS week, all of the shift registers are set to their initial states simultaneously, as shown in Table 4.4. Also, at the end of each X1A epoch, the X1A shift register is reset to its initial state. At the end of each X1B epoch, the X1B shift register is reset to its initial state. At the end of each X2A epoch, the X2A shift register is reset to its initial state. At the end of each X2B epoch, the X2B shift register is reset to its initial state. The outputs (stage 12) of the A and B registers are combined by an exclu-
Phase select logic
1 2 3 4 5 6 7 8 9 10
÷10 Set to
"all ones"
1 2 3 4 5 6 7 8 9 10
X1 epoch
÷20
G epoch 1 KHz 50-Hz data clock
C/A code Gi(t) G1(t)
G2(t + di Tg) 10.23-MHz
clock
. . . .
. . . .
. .
1.023 MHz clock
1.023-MHz clock G1 register
G2 register
X1 epoch
X1 epoch
C R
R
C 1023 decode
Figure 4.10 C/A code generator.
sive-or circuit to form an X1 sequence derived from X1A ⊕ X1B, and an X2 sequence derived from X2A⊕X2B. The X2 sequence is delayed byichips (corre- sponding to SVi) to form X2i. The P code for SVi is Pi=X1⊕X2i.
X1A Register
1 6 12
4092
decode ÷3750
A
⊕ 6, 8, 11, 12
X1B Register
1 12
4093 decode B
⊕ 1, 2, 5, 8, 9, 10, 11, 12
Clock Input
Reset Set X1A epoch
Clock
control ÷3749
Resume Halt
X1 epoch
Z-counter 403200
÷
7 day reset
X2A Register
1 12
4092 decode C
⊕ 1, 3, 4, 5, 7, 8,
9, 10, 11, 12 Clock control
÷3750
Halt End / week
X2B Register
1 2 12
4093 decode Clock
control
÷3749 Halt
End / week
÷37 clock
⊕ 2, 3, 4, 8,
9, 12
C
Shift register clock
B A
1 37
X2i X1
Pi
X2 start / week
X2 epoch Resume
Enable 10.23 MHz
Clock Input
Reset Input
Clock
Reset Clock
Input .. .
.. . . .
.. .
. ..
Set X1B epoch
Set X2A epoch
Set X2B epoch .
..
... .
.
i
. . .
. .. Reset
Note: Reset = reset to initial conditions on next clock.
Note: Reset = reset to initial conditions on next clock.
Figure 4.11 P code generator.
There is also a phase precession between the X2A/X2B shift registers with respect to the X1A/X1B shift registers. This is manifested as a phase precession of 37 chips per X1 period between the X2 epochs (shown in Figure 4.11 as the output of the divide by 37 counter) and the X1 epochs. This is caused by adjusting the X2 period to be 37 chips longer than the X1 period. The details of this phase precession are as fol- lows. The X1 epoch is defined as 3,750 X1A cycles. When X1A has cycled through 3,750 of these cycles, or 3,750×4,092=15,345,000 chips, a 1.5-second X1 epoch occurs. When X1B has cycled through 3,749 cycles of 4,093 chips per cycle, or 15,344,657 chips, it is kept stationary for an additional 343 chips to align it to X1A by halting its clock control until the 1.5-second X1 epoch resumes it. Therefore, the X1 registers have a combined period of 15,345,000 chips. X2A and X2B are con- trolled in the same way as X1A and X1B, respectively, but with one difference: when 15,345,000 chips have completed in exactly 1.5 seconds, both X2A and X2B are kept stationary for an additional 37 chips by halting their clock controls until the X2 epoch or the start of the week resumes it. Therefore, the X2 registers have a combined period of 15,345,037 chips, which is 37 chips longer than the X1 registers.
Note that if the P code were generated by X1⊕X2, and if it were not reset at the end of the week, it would have the potential sequence length of 15,345,000 × 15,345,037=2.3547 ×1014chips. With a chipping rate of 10.23×106, this sequence has a period of 266.41 days or 38.058 weeks. However, since the sequence is trun- cated at the end of the week, each SV uses only one week of the sequence, and 38 unique one-week PRN sequences are available. The sequence length of each P code, with the truncation to a 7-day period, is 6.1871×1012chips. As in the case of C/A code, the first 32 PRN sequences are reserved for the space segment and PRN 33 through 37 are reserved for other uses (e.g., pseudolites). The PRN 38 P code is sometimes used as a test code in P(Y) code GPS receivers, as well as to generate a ref- erence noise level (since, by definition, it cannot correlate with any used SV PRN sig- nals). The unique P code for each SV is the result of the different delay in the X2 output sequence. Table 4.3 shows this delay in P code chips for each SV PRN num- ber. The P code delays (in P code chips) are identical to their respective PRN num- bers for the SVs, but the C/A code delays (in C/A code chips) are different from their PRN numbers. The C/A code delays are typically much longer than their PRN num- bers. The replica C/A codes for a conventional GPS receiver are usually synthesized by programming the tap selections on the G2 shift register.
Table 4.3 also shows the first 10 C/A code chips and the first 12 P code chips in octal format, starting from the beginning of the week. For example, the binary
Table 4.4 GPS Code Generator Polynomials and Initial States
Register Polynomial Initial State
C/A code G1 1+X3+X10 1111111111
C/A code G2 1+X2+X3+X6+X8+X9+X10 1111111111
P code X1A 1+X6+X8+X11+X12 001001001000
P code X1B 1+X1+X2+X5+X8+X9+X10+X11+X12 010101010100 P code X2A 1+X1+X3+X4+X5+X7+X8+X9+X10+X11+X12 100100100101 P code X2B 1+X2+X3+X4+X8+X9+X12 010101010100
sequence for the first 10 chips of PRN 5 C/A code is 1001011011 and for the first 12 chips of PRN 5 P code is 100011111111. Note that the first 12 P code chips of PRN 10 through PRN 37 are identical. This number of chips is insignificant for P code, so the differences in the sequence do not become apparent until later in the sequence.