5.3 Carrier Tracking Loops
5.3.3 Frequency Lock Loops
happens, the ambiguity must be resolved again. The 180º ambiguity of the Costas PLL can be resolved by referring to the phase detection result of the data bit demod- ulation. If the data bit phase is normal, then the carrier Doppler phase indicated by the Costas PLL is correct. If the data bit phase is inverted, then the carrier Doppler phase indicated by the Costas PLL phase can be corrected by adding 180º.
Costas PLLs as well as conventional PLLs are sensitive to dynamic stress, but they produce the most accurate velocity measurements. For a given signal power level, Costas PLLs also provide the most error-free data demodulation in compari- son to schemes used with FLLs. Therefore, this is the desired steady state tracking mode of the GPS receiver carrier tracking loop. It is possible for a PLL to close in a false phase lock mode if there is excess frequency error at the time of loop closure.
Therefore, a well-designed GPS receiver carrier tracking loop will close the loop with a more dynamically robust FLL operated at wideband. Then it will gradually reduce the carrier tracking loop bandwidth and transition into a wideband PLL operation in order to systematically reduce the pull-in frequency error. Finally, it will narrow the PLL bandwidth to the steady state mode of operation. If dynamic stress causes the PLL to lose lock, the receiver will detect this with a sensitive phase lock detector and transition back to the FLL. The PLL closure process is then repeated.
interval (t2 t1) in seconds, are also divided by 4 to more accurately approximate the true input frequency error. The ATAN2 (x,y) function returns the answer in radi- ans, is converted to degrees, divided by the sample time interval (t2−t1) in seconds, and is also divided by 360 to produce at its output a true representation of the input frequency error within its pull-in range. The amplitudes of all of the discriminator outputs are reduced (their slopes tend to flatten), and they tend to start rounding off near the limits of their pull-in range as the noise levels increase.
TheI, Qphasor diagram in Figure 5.12 depicts the change in phase,φ2−φ1, between two adjacent samples ofIPSandQPS, at timest1andt2. This phase change over a fixed time interval is proportional to the frequency error in the carrier track- ing loop. The figure also illustrates that there is no frequency ambiguity in the GPS receiver FLL discriminator because of data transitions, provided that the adjacentI andQsamples are taken within the same data bit interval. However, it is possible for the FLL loop to close with a false frequency lock in a high dynamic environment.
For this reason, very short predetection integration times (wider pull-in range) are important for initial FLL loop closure. For example, if the search dwell time was 1 ms or 2 ms, then the initial predetection integration time in FLL should be the same.
Note that with a FLL, the phasor,A, which is the vector sum ofIPSandQPS, rotates at a rate directly proportional to the frequency error (between the replica carrier and the incoming carrier). When true frequency lock is actually achieved, the vector stops rotating, but it may stop at any angle with respect to theI-axis. For this rea- son, coherent code tracking, as will be discussed in the following section, is not pos- sible while in FLL because it depends on theIcomponents being maximum (signal plus noise) and theQcomponents to be minimum (noise only) (i.e., in phase lock).
It is possible to demodulate the SV data bit stream in FLL by a technique calleddif- ferential demodulation.Because the demodulation technique involves a differentia-
Table 5.4 Common Frequency Lock Loop Discriminators Discriminator Algorithm
Output
Frequency Error Characteristics cross
t t (2− 1) where:
cross=IPS1 QPS2–IPS2×QPS1
sin[(φ2 φ1)]
2 1
−
− t t
Near optimal at low SNR.
Slope proportional to signal amplitude squaredA2. Least computational burden.
( ) ( )
( )
cross sign dot t t
×
−
2 1
where:
dot=IPS1 IPS2+QPS1 QPS2
cross=IPS1 QPS2−IPS2×QPS1
sin[ (2 2 1)]
2 1
φ −φ
− t t
Decision directed.
Near optimal at high SNR.
Slope proportional to signal amplitudeA.
Moderate computational burden
ATAN dot cross t t
2
2 1
( , )
( − )
φ2 φ1
2 1
−
− t t
Four-quadrant arctangent.
Maximum likelihood estimator.
Optimal at high and low SNR.
Slope not signal amplitude dependent.
Highest computational burden.
Usually table lookup implementation.
Note:Integrated and dumped prompt samplesIPS1andQPS1are the samples taken at timet1, just prior to the samplesIPS2andQPS2taken at a later timet2. These two adjacent samples should be within the same data bit interval. The next pair of samples are taken starting (t2– t1) seconds aftert2(i.e., noIandQsamples are reused in the next discriminator computation).
tion (noisy) process, detecting the change in sign of the phasor in a FLL is noisier than detecting the sign of the integrated (lower noise)IPSin a PLL. Therefore, for the same signal quality, FLL data detection has a much higher bit and word error rate than PLL data detection.
sign(dot)(cross) cross ATAN2(dot,cross) Predetection integraton time = 5 ms
(a)
−20
−100
−80
−60
−40 0 20 40 60 80 100
−120 −100 −80 −60 −40 −20 0 20 40 60 80 100 120 True input frequency error (Hz)
FLLdiscriminatoroutput(Hz)
−50
−40
−30
−20
−10 0 10 20 30 40 50
−60 −50 −40 −30 −20 −10 0 10 20
(b)
30 40 50 60
True input frequency error (Hz)
sign(dot)(cross) cross ATAN2(dot, cross) Predetection integration time = 10 ms
FLLdiscriminatoroutput(Hz)
Figure 5.11 Comparison of frequency lock loop discriminators: (a) 5-ms predetection integration time, and (b) 10-ms predetection integration time.