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When Interconnects are NOT Transparent

Signal Integrity and Interconnects

3.2 When Interconnects are NOT Transparent

When are interconnects not transparent? The answer is, as is the most common answer for all engineering questions, “it depends.”

But it is not enough to say it depends. For engineers, the very next sentence must state what it depends on, and, using simple estimates, provide some metric of under what conditions upon which it

depends. This is the essence of engineering.

Of course, all the details of the circuits and the nature of the interconnects affects this boundary of when interconnects are transparent, but we can make a very rough estimate.

An important principle in engineering we will use over and over again is “Sometimes an OK answer NOW! is more

important than a good answer later.”

Even though the real problem is complicated and depends on many factors, sometimes we just want to get a rough idea of when an effect might be important. This is when simplifying assumptions and rules of thumb are incredibly valuable in providing a rough estimate, quickly.

3.2 When Interconnects are NOT Transparent 61

The two most important noise sources that will usually become large enough to be a concern are each a type of switching noise, noise that arises when one or more signals change state and their currents turn off or on.

One type of switching noise is found on the power rail and is caused by the changing power rail currents passing through the power lead inductance between the IC power pins and the voltage regulator module (VRM) or the nearest decoupling capacitor. The VRM is the component that provides the regulated voltage to the power rail on the board. This type of noise is specifically called power rail collapse.

The second type of switching noise is found on signal paths and is generated due to changing return currents passing through the higher inductance of a return path that is not a wide, continuous plane. It increases with more signals sharing the same return conductor and switching simultaneously. We refer to this sort of noise as ground bounce.

This is noise generated by multiple signals changing their state with all of their return currents passing through the same, narrow conductor. This happens in IC packages, in connectors, in some multiconductor cables, in solderless breadboard interconnects, and in circuit boards with poorly designed return paths.

It is fundamentally due to the changing or switching currents passing through the shared inductance of a common return path. An example of ground bounce noise on a victim line with one, two, three, and then four I/Os switching simultaneously through traces on a board with a shared return trace is shown in Figure 3.3.

Figure 3.3 Measured 5 V signal on the aggressor trace (top) and the measured induced noise on the victim trace (bottom) when an increasing number of aggressor signals switch. This is a form of cross talk, specifically ground bounce or simultaneous switching

noise.

Using a few simplifying assumptions, we can estimate when ground bounce noise may be a problem.

The voltage noise across the inductance of an interconnect is:

(

Len

)

V L Len I RT

 =   

Where

V = the voltage noise generated, mV

LLen = the inductance per length of the interconnect, nH/in Len = the length of the interconnect, in

I = the change in current or the transient current, mA RT = the rise time of the changing current, nsec

If we call a transparent interconnect when the induced voltage noise is below some maximum acceptable level, then the relationship between the longest length that is still transparent is,

3.2 When Interconnects are NOT Transparent 63

max transparent

Len

V

Len 1 RT

L I

  

 Now we can put in some numbers.

For simple interconnect wires, the inductance per length is about 20 nH/inch. If we say voltage noise less than 50 mV is insignificant when there is 50 mA of current change, the criterion of transparent interconnect becomes:

     

   

transparent

transparent

1 50mV

Len in RT n sec

20 nH / in 50mA Len in 0.05 RT n sec

  

 

This rule of thumb says that if the shortest rise time of a signal in a circuit is 100 nsec, interconnects shorter than 5 inches will look transparent. They will have negligible noise, and how we route the signals and return paths in the solderless breadboard or the circuit board will have little impact on the performance of the circuits. This criterion defines two regions of design space, when interconnects are transparent and when the design of the interconnects matter.

This is illustrated in Figure 3.4.

Figure 3.4 Mapping the design space where interconnects are transparent (lower triangle) and interconnect design is not important for this set of assumptions.

Most solderless breadboards have wires less than about 10 inches long. This suggests that as long as signal rise times are longer than about 200 nsec, the interconnects in solderless breadboard circuits will be transparent. This is a very useful rule of thumb.

But this is a very conservative estimate. If the current changing in a circuit is not 50 mA, but goes up to 500 mA, the length condition for transparent interconnects is reduced by a factor of 10. For a rise time of 200 nsec, any interconnect shorter than only 2 inches would be transparent.

In addition, even if there is significant switching noise, if it occurs at a time at which the circuit is not sensitive, it may not be important.

This is why so many circuits work when implemented in a solderless breadboard or in a circuit board despite following no signal integrity design guidelines or following inappropriate guidelines: the

interconnects are transparent, or the signals are insensitive to the noise levels generated.

By following best design practices using solderless breadboard interconnects, it may be possible to extend their useful range into rise times as short as 2 nsec if interconnect lengths can be kept short.

Figure 3.5 shows the measured signal from a small micro controller module plugged into a solderless breadboard with a measured 10-90 rise time as short as 1.95 nsec using a short interconnect.

Figure 3.5 A Teensy 4.0 module in a solderless breadboard measured with a high bandwidth probe and 8 GHz bandwidth Teledyne LeCroy WavePro HD scope. The

measured rise time is 2 nsec.