CHAPTER V
SINGLE EVENT EFFECTS CHARACTERIZATION AND MITIGATION IN DLLS
single event transients. The voltage charge pump is an attractive technique because it is area efficient and would improve the locking time of the PLL. An increase in phase jitter is the main tradeoff of the implementation of the VCP over the current charge pump. Simulations, using double exponential current pulses for charge deposition up to 500 fC show that the VCP can significantly reduce the number of erroneous pulses generated by an ion strike within the PLL.
Fig. V-1 Maximum number of erroneous pulses resulting from strikes of energy 30 nJ, in various PLL components, validating experimentally the voltage charge pump as a hardening technique
for digital PLLs, the number of erroneous pulses is reduced by 2 orders of magnitudes.
CP represents the charge pump of the PLL, V-CP is the voltage charge pump and VCO is the voltage controlled oscillator [14].
Furthermore, experimental validation of the simulation results using a two photon absorption (TPA) laser technique on the PLL implementing the VCP show a dramatic reduction in the number of erroneous pulses generated at the output of the PLL, when compared with the experimental result of the PLL implementing the current charge pump, as shown in Fig V-1 [14].
Based on the experimental results, it would be very interesting to investigate the exportability of such a hardening techniques to reduce the SET sensitivity of the charge pump in analog DLLs.
In [16], the author reduces the single event effects sensitivity of the PLL by targeting the bias stage of the VCO, through redundancy. Since the input-bias stage of the VCO controls the output frequency of the PLL, an ion strike in the bias circuit will result in a control voltage perturbation and thus generates an erroneous frequency modulation of the output signal of the VCO. This control voltage perturbation can be eliminated by replicating it several times and averaging the output using identical resistors in the bias circuit as shown in Figure V-2, thereby minimizing any perturbation due to an ion strike [16]. Simulations results show that duplicating of the bias stage reduced the phase displacement error at the output of the PLL by 35%.
Fig. V-2 Schematic of the VCO implementing the analog redundancy hardening technique applied to the bias stage [16].
In [42], D. Matsuura et al. propose a radiation hardened PLL, where the triple modular redundancy hardening technique is applied to the VCO, as illustrated in Figure V-3. In addition,
since the voltage perturbation derived from the current induced by ion strike lead to frequency modulation of the output clock, the author inserts an additional transistor in series with each transistor of the delay cell, to decrease the induced current.
Fig. V-3 Schematic block diagram of the RHBD PLL proposed in [42].
Similar hardening solutions, based on the VCO or CP redundancy to harden the PLL, can be found in the literature [42, 43, 48]. In [44], a radiation hardened PLL design is proposed using a VCO design based on two current-starved ring oscillator structures, with cross-coupled signals, that help to ensure that the effect of an ion strike on one ring is compensated by the other ring is proposed. As in [42, 43] the hardened design also comes with significant area penalty.
As mentioned earlier, extensive studies on SEEs in PLLs are available in the literature, but there is a dearth of such studies for DLLs. In this PhD work, we are proposing to remedy this knowledge gap by investigating and developing hardening techniques for analog delay locked loops. The next section will be devoted to the background work on SEEs in DLLs.
In their work, R. Sengupta et al. proposed a radiation-hardened digital DLL, in [8]. The proposed 133 MHz DLL is illustrated in Figure V-4. In the proposed DLL, all mixed-signal components are replaced with digital circuit blocks. As an example the charge pump is replaced by a digital integrator. In [8], the all-digital DLL is then hardened using error-correction logic and triple modular redundancy (TMR) techniques, known for the associated power and area penalties.
In addition, those solutions are non-innovative in terms hardening techniques. In the hardened all- digital DLL, an ion strike in the master-slave architecture will always generates a reliable output, even if any of the circuit blocks have been struck by an ionizing particle, causing either SETs or SEUs. These results were achieved by protecting with TMR the slave delay line and the error correction logic (ECL), which feeds into the slave delay lines. In addition, multiple bit upsets (MBUs) in the digital-loop filter were mitigated by interleaving the layout. The power and area penalty of the radiation-hardened DLL are 32% and 37%, respectively. The circuit design and layout were completed on the TSMC 130-nm process. While the authors claims that a similar architecture can be used for designing radiation-hardened digital PLLs, circuits very different in their topology (c.f. Figure II-4(b) and Figure V-4), this document relies on simulation results obtained with CADENCE ADE tools and does not present any experimental data to validate the RHBD ADDLL design. In addition, this study does not propose a new hardening technique, since the hardened ADDLL design uses the most common RHBD technique: TMR.
Fig. V-4 133MHz radiation hardened all-digital DLL, using TMR to harden the error correction logic and slave delay line [8]