Simulation Results of the ECC

C. Hardening Technique 2: The Clock Error Correction Circuit

3. Simulation Results of the ECC

Fig. VI-35 RTL schematic of the ECC implemented with the missing-pulse injection block and the DCM/DLL. The outputs and inputs of the circuit are monitored using the Xilinx ChipScope Pro

Analyzer tool.

(a)

(b)

Fig. VI-36 Worst case SET response (in terms of missing pulses and phase error) generated by peeled VCDL (outputs Op1, Op2) and the ECC (Vout) at LET = 100 Mev-cm²/mg for a) a hit in

Op2/On2, b) a hit in Op1/On1, Only 15% duty cycle variations are observed following the switching operation of the MUX. In all cases, no missing pulses were observed at the output of

the ECC or DLL.

Ion strike

Ion strike

Figure VI-36 illustrates the worst-case phase displacement error generated by the ECC when implemented with a peeled VCDL layout at LET = 100 MeV-cm²/mg. The transient responses of the outputs Op1 and Op2 and the outputs of the DLLs (Vout) are compared. Figure VI-36 (a) represents the case where Op2 is perturbed and two missing pulses are generated. However, no missing pulses are observed at the DLL output Vout, and therefore no errors were propagated into the clock system. Figure VI-36 (b) represents the case where Op1 is perturbed and two missing pulses are generated. As in the first case, the missing pulses are filtered at the output of the DLL, Vout. Note that a duty cycle variation is observed for a few clock periods, caused primarily by pulse skew following the switching operation of the MUX. By using transmission gate based XOR gates, this ECC design penalty was minimized to a 15% duty cycle variation.

Simulations at LET = 100 MeV-cm²/mg show that ion strikes have a very small impact on the error correction circuit itself. Any strike on the XOR can only temporarily ‘flip’ the logic state of the signal Sel, forcing the ECC to toggle between two identical MUX inputs, so the MUX output signal remains the same with no upset propagated into the clock network. A strike in the MUX has a 50% chance to be propagated to the output of the ECC depending on the internal MUX signal path. In the worst case, the ion strike will generated a duty cycle error for less than a clock cycle in the output signal Vout of the ECC (c.f. Figure VI-37), equivalent to a phase displacement of 1.4 radians at 1 GHz in a 40 nm process. Considering jitters, one of the disadvantages of XOR gates (phase detectors) is that the voltage output signal varies with the duty cycle of the input signals. Thus the XOR gates used in the error detection block may increase jitter at the output of the DLL that could be fed back into the circuit. As long as the phase detector does not capture jitter, the stability of the DLL is ensured. In the 40 nm design, the dead zone of the phase detector is approximately 80 ps, therefore jitter (less than 40 ps with the additional ECC block) were not captured by the PD and the stability of the DLL in lock state was

not compromised. Guidelines to improve the jitter response of the circuit would be to use AND- OR-Invert (AOI) XOR gates with less logic and fast operation, decrease the charge pump current (i.e. decrease the gain of the phase detector) [18] or use a toggle in the ECC block (this solution may increase the ECC block logic complexity).

The additional area and power required by the ECC is not significant, particularly when compared to the area and power requirements of the other DLL sub-circuits. Therefore, this new error correction technique provides an excellent tradeoff between SET response and area-power penalty. The area penalty is less than 2% for the entire DLL, as compared to triple modular redundancy of the VCDL with an area increase of approximately 30%.

Fig. VI-37 Worst case SET following a strike in the 2:1 MUX of the ECC block, at LET =100 MeV-cm²/mg. One clock cycle duty-cycle error was recorded at the output of the DLL

(Vout – ECC/DLL) for strikes in the error detection block.

Figure VI-38 compares the SET response of a 1 GHz DLL with the ECC (implemented in 180 nm, 90 nm and 40 nm technology nodes) with the original hardened complementary diff. pair VCDL [2]. The missing pulses generated by an ion strike within the DLL implementing a hardened complementary diff. pair VCDL (RHBD_DLL) or the DLL implementing the ECC hardening technique (ECC_DLL) are significantly reduced or mitigated when compared to the SE response of the DLL using an unhardened VCDL (unhardened_DLL). Simulations at high LETs show that the ECC_DLL also mitigates missing pulses at the 40 nm technology node, with even worst-case simulations showing only duty cycle errors.

These results lead to the conclusion that both hardening techniques are effective for mitigating missing pulses at frequencies below 1 GHz in 90 nm and 180 nm technologies.

However, the duty cycle error of the ECC hardened DLL remains approximately constant as

frequency increases, with no missing pulse observed at 1 GHz, demonstrating that this new hardening technique is both effective and scalable.

Fig. VI-38 1 GHz DLL maximum phase error vs. technology node for worst-case LET = 100 MeV.cm²/mg within the unhardened DLL implementing the current starved VCDL, the DLL

implementing the hardened compl. diff. pair VCDL (RHBD_DLL) and the hardened DLL implementing the ECC technique (ECC_DLL). The ECC mitigates missing pulse(s) in a 40 nm

technology at 1 GHz, and is similarly effective in other technology nodes. The number in the parenthesis represents the missing pulses generated by the VCDL [76]