Cross section of nFET TCAD model showing cut lines 1 and 2 shown for Fig. a) Layout view of nFET TCAD model with section line for Fig. b) Cross section of nFET TCAD model taken along cutting line in Fig. Boron doping concentrations of p-well contact along cut line 3 in Fig. Cross section of pFET TCAD model showing section lines 4 and 5 used for Fig. a) Layout view of pFET TCAD model with cut line for (b) shown.
Overview
Overview of previous work
Consequently, restoring current is very important parameter that controls the SE response of a circuit. In this thesis, both the negative and positive effects of charge sharing in combinational logic cells are investigated.
Statement of research problem and overview of thesis
All of these previous works focus on either circuit-level simulation or testing to characterize SETs in cell libraries, whereas this work focuses on the mechanisms governing the SE response of digital library cells. process of the library characterization, many critical aspects of charge collection by devices in 90 nm bulk CMOS were investigated. The author states that in the simulation of the high injection of a heavy ion strike, "the carrier-carrier model represents the largest source of uncertainty".
DEVICE MODELS
Compact modeling
The collected charge of the pFETs increases dramatically (up to 220%) with inverter size, while the nFETs show a modest increase (up to 30%). The width of the n-well (2 µm) corresponds to the vertical dimension of the region shown in Fig.
BASIC SINGLE-EVENT SIMULATION
Ion strike on p+ diode
As expected, the sum of these charges is zero, with the magnitude of the positive or negative charge equal to the charge deposited by the ion as electrons and holes are released in pairs. Since the attack had a normal incidence, this length corresponds to the depth of the sensitive area, which is physically the depth.
Ion strike on unloaded pMOSFET
The two active collectors in the pFET structure are the p-drain (CD) and the buried p-well/latchup profile (CW). Since the drain/n-well diode has collected 180 fC of hole charge without the source, the number of source-injected holes collected by the drain is about fC.
Ion strike on pMOSFET in mixed-mode inverter
Because the nFET limits the drain current to 230 µA, the collected charge is limited and therefore much smaller than with the unloaded pFET. Finally, the qualitative differences can be discussed by plotting the runoff flows from each of the three simulations.
Conclusion
Both of the 75° strikes show an increase in pulse width with drain area (as before, the 75° strikes enter exactly 200 nm from the edge of the diffusion for each size of drain area). R2 is the vertical resistance from the bulk of the n-well to the top of the n-well contact.
SINGLE-EVENT RESPONSE OF MULTIPLE-
Simulation setup
To simulate nFET hits (n-hits), the nFET was modeled in 3-D TCAD, while the current-matched pFET was modeled in Spice using a calibrated compact model. For p-hits, the pFET was modeled in TCAD and the nFET was modeled in Spice.
Constant drive strength
The percentage change in collected charge is plotted as a function of the number of fingers for nVEOs in Fig. Conversely, Drain 2 does collect charge from 60° strikes, so collected charge increases with number of fingers.
Varied drive strength with constant finger width
The total drain current is the sum of the two drain currents for 3 and 4 finger devices. This is the only reason for the increase in charge collected by nFET as the size of the inverter increases. The charge collection of Drain 2 helps explain why the charge collected by pFET increases dramatically with the size of the inverter.
28(a), the trough of the n-hit pulses approaches half-VDD as the inverter size is increased.
Conclusion
As described in Chapter 3, the n-well acts as the bottom of the parasitic bipolar device shown in Fig. Both the sensitive area and the average pulse width are smaller than the p-hit values due to the larger size of the pFETs and the parasitic bipolar amplification in the pFET structure [8]. The effect of the well doping is different depending on the LET, as shown in Figure 74.
This result is because the main effect of higher n-well doping per single event is a decrease in the resistance between the device and the n-well contact.
CRITICAL FACTORS IN SINGLE-EVENT RESPONSE
Diode area
The shocks were initially simulated with LET of 5 MeV-cm2/mg, and the resulting collected charge is plotted against diode area in Fig. Normal taps show very little change in the collected charge relative to the diode area; however, the 75° strikes show variation from 12 to 50 fC, a 317%. Since the charge collected by the n-well contact indicates the deposited charge, this graph shows the increase in deposited charge as the diode area increases.
In this case, the variations in path length dominate the correlation between diode area and accumulated charge.
Drain area
Simulations are performed varying the drain area while keeping the source area constant at 0.27 µm x 0.84 µm ≈ 0.23 µm2. The charge deposited by the angled abutments increases with drain area because the length of the abutment path increases, and the charge collected by the drain increases because the charge is deposited along the plane of the junction. The effect of the source area on the SET pulse width is not as dramatic as the drain area.
In summary, since the lateral BJT primarily controls the drain total charge and does not depend on the source area, the effect of the source area on the SET pulse width is minimal.
Restoring current
The pFET TCAD model remains unchanged while the n-channel width is varied to change the recovery current to the pFET. Although the affected device is identical in all simulations, the collected charge shows large variations when the pull-down nFET width is changed. When the recovery current is increased, more charge is collected from the affected device at a given time, as shown by the increasing current in Figure 2.
Thus, the total charge to the drain of the pFET increases as the recovery current increases.
N-well contact area and location
Figures 43(a) and (b) from [21] show how the SET pulse width varies with n-well contact area and distance, respectively. When considering the variations in a cell library, the n-well contact area is typically the same for all cells. In the cell library characterized in this work, the well contact area, and thus R2, is identical for all cells.
In general, well contact area and spacing have a strong effect on pFET SE response, but at the scale of a digital cell library there is little or no variation in these parameters.
![Fig. 43: (a) Effect of n-well contact area on SET pulse width. This shows how R2 influences the pFET SE response; after [21]](https://thumb-ap.123doks.com/thumbv2/123dok/10731075.0/67.918.167.804.728.996/fig-effect-contact-pulse-width-shows-influences-response.webp)
Conclusion
This chapter describes the basic methodology and results of characterizing single-event transients in a 90-nm bulk CMOS RHBD digital cell library containing approximately 500 cells. Worst-case single-event transitions are identified and parameterized in the logic cells using TCAD. Such 3D simulations are very time and computer resource intensive, often requiring tens of hours for one single-event simulation.
Standard TCAD single-event (SE) simulation on all device and circuit variants for all cells is difficult or impossible.
Worst-case SET simulation setup
By focusing on worst-case single-event transient (SET) cases, based on known critical factors and parameterized trends in SET characteristics for the baseline technology, single-event library characterization is simplified and the total simulation time of an event is reduced to a manageable level. level. This method is presented along with simulation results showing worst-case SE sensitivity comparison of all logic cells. Once you have identified the worst-case shock parameters for an individual transistor, the next step is to determine the worst-case circuit input state for the cell, i.e.
44: (a) Worst-case pFET impingement at 75° along the n-well, (b) Schematic of a 3-input NOR gate showing charge-collecting nodes in the worst-case input state.
Simulation results and discussion
Comparison to experimental data
Heavy ion and proton experiments were performed on inverter, NAND and NOR cells in the digital library in [23]. Many of the observations made in the simulations of this work were also made in the experimental results. In particular, the competition between sensitive drain area and driving force is discussed when comparing the SE response of different cells.
For a given scale factor, the inverter's driving current is larger than in any other cell, and the inverter's sensitive drain area is smaller than in any other cell.
Conclusion
Both the sensitive areas and the average pulse width of the 75° and 40 MeV-cm2/mg shocks show dramatic reduction from node X to node Y. Due to the pulse cancellation between the NAND stages and the AND gate inverter, as the sensitive area and the average pulse width can be dramatically reduced. In this section, a design is proposed that promotes pulse cancellation between the two logic stages of the AND gate.
Assuming that each input combination is equally likely, damping of the pulse in the AND gate can occur only 25% of the time.
EFFECT OF SINGLE-EVENT STRIKE LOCATION AND
- Simulation setup
- Simulation results: pFETs
- Simulation results: nFETs
- Single-event transient mitigation using pulse quenching
- Conclusion
CONCLUSIONS
CARRIER-CARRIER SCATTERING MODELS FOR SE SIMULATION
In [26], two commonly used carrier-carrier scattering models, the Philips model and the Dorkel-Leturcq model, were compared for applicability to SE simulation. There are four carrier-carrier scattering models available in the TCAD simulator SDevice: Conwell-Weisskopf (basically the same as the Dorkel/Leturcq), Brooks-Hering, Philips unified model that Klaassen uses, and Philips unified model that Meyer uses [17] . The result of the Conwell-Weisskopf model's low mobility is a longer current and voltage transition; the SET pulse width is double the pulse without any carrier-carrier scattering.
Roughly speaking, the uncertainty in the pulse width due to carrier scattering can be limited by the variations seen in Figure 72.
EFFECTS OF DOPING VARIATIONS ON SETS
The calibration of the TCAD models can be verified against (matched within 10%) the IBM CMOS9SF Spice models available from the MOSIS service [19]. The presence of the source also affects the other terminals compared to the diode simulation. For example, if a wide pFET is required for a design, it may be limited by the width of the n-well.
Both the p-well and the n-well were contacted with strip contacts along the entire length of the well surface. Figure 29(b) shows the cross section of the diode model, taken from the cut line in Fig. The amount of expansion depends on the de-anization of the well n, which depends on the contact scheme of the well, i.e.
