3. AFA-based Approximate Adders
Bi+1 Ai
Bi Ai+1
B1 A1
B0 A0
Cin0
S0 S1
SN−1 Si CoutN−1
Si−1 Si+1
Bi−1 Ai−1 A
B N−1
N−1
AFA AFA
AFA AFA
AFA
#1
#1
#1
#1
#1 AFA #1
Figure 3.4: Generalized architecture of anN-bit ApproxADD designed by cascadingN AFA#1 in series.
RCA can be given by:
Dnm = DAF A#1
DF A[S]+ (N −1)×DF A[Cin:Cout]
= 12
13.33 + (N −1)×9.66 = 1.2422
N + 0.3799 (3.14)
where,DAF A#1is the delay to compute sum in AFA#1,DF A[S]is the delay to compute sum in conven- tional FA andDF A[Cin:Cout]is the delay to compute carry propagation (Cin → Cout) in conventional FA. Further, using Table 3.3 and Table 3.4, the normalized dynamic power consumption (Pnm) and normalized area (Anm) of an ApproxADDw.r.t.RCA can be given by:
Pnm = N ×Pnm invAF A#1
N ×Pnm invF A
= 0.5275 (3.15)
Anm= N ×AAF A#1
N ×AF A
= 0.7143 (3.16)
where,Pnm invF AandPnm invAF A#1 are the normalized dynamic power consumptions of conventional FA and AFA#1w.r.t.a unit standard CMOS inverter, andAF AandAAF A#1are the areas of conven- tional FA and AFA#1, respectively.
3.3.2 ED and ER Estimation
As shown in Table 3.2, AFA#1 provides erroneous carry for two out of eight input combinations.
These two input combinations are A.B.Cin and A.B.Cin. Further, in ApproxADD, Cini is Ai−1. Therefore, in ApproxADD, an erroneous carry generates atithbit position only whenAi.Bi.Ai−1 = 1
3.3 ApproxADD
orAi.Bi.Ai−1 = 1. We know that in addition operation, erroneous carry generated atithbit position affects the output at(i+ 1)th bit position. Accordingly, ED of an ApproxADD can be given by the weighted sum of input combinationsAi.Bi.Ai−1 andAi.Bi.Ai−1as:
ED≈
N−1
X
i=0
2i+1×
(Ai.Bi.Ai−1) + (Ai.Bi.Ai−1)
(3.17) where,·and+represent the binary AND and OR operations, respectively. Note that in ApproxADD, either of the input combination (Ai.Bi.Ai−1 or Ai.Bi.Ai−1) can not occur consecutively. However, these input combinations can occur in an alternative fashion. This is the worst-case in which Approx- ADD provides maximum error. For example, let us assume thatA is01010101, B is10101010and Cin0 is0. In this case,Ai.Bi.Ai−1 ORAi.Bi.Ai−1 is11111111, which implies that if we addAandB using ApproxADD, then error will occur at all bit positions. Since accurate sum is11111111, approx- imate sum (computed using ApproxADD) should be00000000. However, ApproxADD computes it as01010101. This difference is because in ApproxADD, two consecutive erroneous carries generated fromithbit position do not propagate erroneous carry for(i+ 2)thbit position. The reason behind this is the fact that twice the complement of a function is the function itself. In other words, an erroneous carry generated atith bit position masks the effect of erroneous carry generated at(i+ 1)thbit posi- tion. Therefore, Eqn. (3.17) can be corrected by subtracting the weighted sum of input combinations which generate consecutive erroneous carries as:
ED ≈
N−1
X
i=0
2i+1×
(Ai.Bi.Ai−1) + (Ai.Bi.Ai−1)
−
N−1
X
i=0
2i+1×
(Ai.Bi.Ai−1).(Ai−1.Bi−1.Ai−2)
−
N−1
X
i=0
2i+1×
(Ai.Bi.Ai−1).(Ai−1.Bi−1.Ai−2)
(3.18) Note that Eqn. (3.18) is still an approximation because overlapping cases are not taken into con- sideration. Further, in most of the error-resilient applications, RED is more meaningful as compared to the absolute ED, where RED is defined as the ED normalized to corresponding correct output
3. AFA-based Approximate Adders
(Rc) [75]. For a set ofn inputs, MRED of an ApproxADD can be given by:
MRED = 1 n
n
X
i=1
REDi = 1 n
n
X
i=1
EDi
Rci
(3.19) Further, in order to model the ER of ApproxADD, we use empirical approach. Note that empirical approaches are generally based on the information received by the means of observation or experi- ence of patterns and behavior through experimentation. As per our experimental observations, ER of ApproxADD forms a Geometric Progression (GP) with scalar factor≈1/4and common ratio≈3/4.
Accordingly, ER of an ApproxADD can be given by:
ER =
N
X
i=1
1 4×
3 4
i−1
=
N
X
i=1
3i−1
4i (3.20)
3.3.3 Simulation Setup
For assessing the simulation results of delay, power and area, we design different configurations of ApproxADD using Mentor Graphics Tanner schematic capture [103]. While designing the schemat- ics, we size all the logic gates to template gate according to minimum-size inverter. We then extract netlists from schematics and simulate the extracted netlists using Synopsys HSPICE circuit simula- tor [104] with Predictive Technology Model 32nm model files [105]. While evaluating the area of ApproxADD, we neglect area imposed by interconnects and extract layout area of the logic gates only from HSPICE netlists. Further, for assessing the quality metrics of ApproxADD, we implement dif- ferent configurations of ApproxADD in C/C++. We simulate each configuration individually for one billion pseudo-random inputs drawn from a sample space between0and2N−1. The same simulation setup is carried-out in the rest of this Chapter.
3.3.4 Results and Discussion
The analytical results and simulation results of ApproxADD as a function of N for normalized delay, power, area and PDAP are shown in Fig. 3.5(a) and for MRED and ER are shown in Fig.
3.5(b). It can be seen from Fig. 3.5(a) that the normalized delay of ApproxADD decreases with bit-width at a rate≈ 1/N. This implies that ApproxADD provides bit-width-aware constant delay
3.3 ApproxADD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Bit−width (N)
Delay Delay Power Power Area PDAP PDAP Simulation Results
Analytical Results
(a)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0.37 0.39 0.41 0.43 0.45 0.47 0.49 0.51
Mean Relative Error Distance (MRED)
Bit−width (N)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Error Rate (ER)
MRED MRED ER ER
Analytical Results Simulation Results
(b)
Figure 3.5: Analytical and simulation results ofN-bit ApproxADD as a function ofN: (a) Normalized (w.r.t.
N-bit RCA) delay, power, area and PDAP; and (b) MRED (on left y-axis) and ER (on right y-axis).
(O(1)). ApproxADD also improves dynamic power consumption by 46.31% and area by 28.57%
w.r.t. RCA. Further, as shown in Fig. 3.5(b), MRED of ApproxADD decreases with bit-width, but for N ≥ 9, it saturates. On the other hand, ER of ApproxADD increases rapidly with bit-width (≈ 1 forN ≥ 13). Here, it should also be noted that the difference between analytical results and simulation results is very small. It means our analytical results agree closely with simulation results.
Further, analytical results and simulation results of area are identical as in both cases, we neglect area imposed by interconnects and consider the area of logic gates only.
3. AFA-based Approximate Adders