proceeds to the next bit position.
(iii) If both input bits are1, then the checking process is stopped and from this bit onwards, all sum bits to the right are set to1.
As shown in Fig. 2.5(b), the modified XOR gate consists of XOR gate, NOT gate and three transistors (M1, M2 and M3). The control signal which is generated by the control block sets the operational mode of the modified XOR gate. WhenCT L= 0, M1 and M2 are turned on, while M3 is turned off, leaving the circuit to operate as normal XOR gate. WhenCT L = 1, M1 and M2 are turned off, while M3 is turned on, connecting theStoVDD, and thus, setting it to1. The function of the control block is to: (i) Detect the first bit position when both input bits are1; and (ii) To set the control signal on this position as well as those on its right to1.
2.4 State-of-the-Art ESAs
In recent years, ESAs has attracted a lot of attention of researchers/designers due to the key fea- tures of design flexibility and programmability. Different from the AFA-based approximate adders, ESA-based approximate adders do not eliminate the entire or a part of the carry-chain. Instead, they split the entire carry-chain into a number of short paths and complete the carry propagations in these short paths concurrently. As shown in Fig. 1.6, in this approach, anN-bit adder is segmented into sev- eral smaller disjoint or overlapping equally sized accurate sub-adders. AnN-bit ESA has two primary design parameters: (i) Segment size (k), which represents the maximum length of carry propagation;
and (ii) Overlapping bits (l), which represents the minimum number of bits used in carry prediction, where1≤k < Nand0≤l < k. Based on the relationship betweenkandl, several ESAs have been proposed in the literature [12, 14, 61–72]. In case of ESAs proposed in [14, 61–67],kneed to be fixed apriori. Further, for a givenk,lis also fixed in these ESAs (l = 0in [14],l =k/2in [62, 64–67] and l =k−1in [61, 63]). Consequently, ESAs proposed in [14, 61–67] can be designed for a given con- figuration, and thus, their design flexibility is limited. On the other hand, ESAs proposed in [12, 69]
provide a very high degree of design flexibility by supporting multiple configurations. However, they provide this feature at the cost of hardware complexity.
2. Literature Survey
80% 60% 40%
100%
Required Accuracy 1.0
Normalized Power
60%
T1 T2 T3 T4
Event Occurred
Time Figure 2.6: Power benefits from accuracy configurable adders.
SN−1:N−r
Cout Sh−1:0
l−bit Prediction
Carry−in
Sub−adder r−bit
r−bit Sub−adder
l−bit Prediction
Carry−in
Sub−adder h−bit
Sr+h−1:h
Figure 2.7: Generalized architecture of anN-bit ACA designed by dynamic tuning ofkandl[12].
Accuracy Configurable Adders: Depending on the requirements of the applications, ESAs are designed for a targeted accuracy. Since different applications have different level of error-resilience, an approximate adder designed for an application can not be used for another application. Therefore, one of the major drawbacks of approximate adders is re-design efforts. Further, sure enough, not all the digital systems can accept the concept of approximate adders. For example, general purpose digital systems which run a variety of applications (including the error-resilient applications) refuse the use of approximate adders. In contexts where the accuracy requirements changes during runtime, the accuracy should be configurable to maximize the benefit of approximate adders. In the literature, such adders are known as ACAs. Fig. 2.6 illustrates how power benefits can be achieved with an ACA.
We know that accuracy of anN-bit ESA depends the primary design parameterskandl. Therefore, as shown in Fig. 2.7, the accuracy of ESAs can be configured by tuningkand/orldynamically using multiplexers. [12, 64, 70]. Multiplexers select carry-in either from the previous sub-adder or from the carry-in prediction. Based on the requirements of the applications, we can combine sub-adders
2.4 State-of-the-Art ESAs
A
B
S S
app
acc S
EF ESA ECL
EDL
EF
Power Gating Switch
Figure 2.8: Generalized architecture of ACAs and VLSAs using EDC logic [13].
together as groups by setting the control signals of multiplexers.
Besides the tuning ofk andl, another approach to configure the accuracy of ESAs is EDC logic [14, 61, 65, 69, 70, 85, 86]. As shown in Fig. 2.8, Error Detection Logic (EDL) detects errors and Error Correction Logic (ECL) corrects them based on the requirements of the applications. Note that EDC logic based ACAs are augmented with an Error Flag (EF) to reduce the power consumption. We know that power gating is one of the most effective approaches used to reduce the power consumption of digital circuits [97]. In this approach, power consumption is reduced by shutting off the current to the circuit blocks that are not in use. In ACAs also, for saving the power consumption, EF signal shuts off the ECL block when ESA provides correct result [65].
Variable Latency Speculative Adders: ESAs integrated with EDC logic can also work as VL- SAs. The design approach of ACAs and VLSAs is similar, but ACAs configure accuracy during runtime based on the requirements of the applications, whereas VLSAs always provide accurate re- sults. In ACAs, EDC logic starts correction errors from the least significant sub-adder and moves toward the most significant sub-adder till the required accuracy is not achieved. On the other hand, in VLSAs, EDC logic corrects errors in all sub-adders. VLSAs take one clock cycle when the ESA provides correct result and take two clock cycles when the ESA provides incorrect result. In this way, VLSAs provide results with variable latency. In recent years, several EDC logic have been proposed in the literature for ACAs and VLSAs [14, 61, 65, 69, 70, 73, 85, 86].
As the underlying structure of ESAs, ACAs and VLSAs is similar, it is not convenience to discuss them separately (like we do in the previous Section for AFAs). Therefore, here, we discuss ESAs, ACAs and VLSAs altogether in a proper sequence as follows.
2. Literature Survey
Sh−1:0
Cout
Sub−adder h−bit
Sub−adder k−bit
Sub−adder
S k−bit
k+h−1:h
SN−1:N−k
Figure 2.9: Generalized architecture of anN-bit DSEC [14].
In the literature, most of the ESAs have been proposed for l = 0 [14], l = k/2[62, 64–67] and l = k − 1[61, 63]. Later in Chapter 4, we discuss some important observations regarding ESAs.
Here, it should be noted that for a fixedk, anN-bit ESA withl = 0provides the lowest ED and with l = k−1, it provides the lowest ER. Therefore, ESAs withl = 0are considered as ED-optimal and ESAs withl =k−1are considered as ER-optimal. On the other hand, ESAs withl =k/2provide trade-off between ED and ER to smooth the overall behavior.
Mohapatra et al. [14] propose an ESA with l = 0, called as Dynamic Segmentation and Error Compensation (DSEC), to exploit the concept of voltage over-scaling. As shown in Fig. 2.9, de- pending on the degree of voltage over-scaling, value ofkcan be configured using the control signals of multiplexers. Under the nominalVDD, multiplexers select the original carry-in and feed it to the subsequent sub-adder. When operating under the voltage over-scaling, sub-adders are isolated from each other due to a carry-in of0being feed by the multiplexers.
Kahng et al. [65] propose an ESA with l = k/2. The authors also present an EDC logic where error correction happens in various stages. The stages can be pipelined for increasing the throughput of the design. Shafique et al. [69] propose a more generalized version of [65], called as Generic Accuracy Configurable Adder (GeAr), which allows the flexible values of k and l. By configuring these parameters, we can control the accuracy of GeAr, however, at the design time only. The authors also provide an EDC logic which is similar to the one proposed in [65]. Note that in [65, 69], the error correction starts from the least significant sub-adder and moves toward the most significant sub-adder. Hence, the accuracy of ACAs proposed in [65, 69] improves slowly in the progression of configurations. In order to overcome this drawback, Benara et al. [73] propose a correction technique