1. Introduction
1.5.3.2 Yield Enhancement
With continued innovations in fabrication process steps, CMOS technology is moving toward finer geometries, exhibiting higher performance, higher energy efficiency and lower silicon area per computation. However, with the relentless scaling of CMOS technology in sub-nanometer regime, chip yield has become a matter of concern for the semiconductor industry due to the fact that profits are tied directly to the chip yield [9]. We explore the effectiveness of approximate adders for yield enhancement. We propose analytical models to estimate the functional yield and parametric yield of approximate arithmetic circuits. From the proposed analytical models we observe that approximate data path modules can improve the functional yield and parametric yield due to decrease in area and delay, respectively. We demonstrate this in respect to ApproxADDs.
1.5.3.3 MAC Unit
Multiply-and-Accumulate (MAC) unit is the heart of multimedia applications. As MAC unit lies in the critical path, it determines the overall delay, power and area of multimedia systems. We know that all basic arithmetic operations, such as addition, subtraction, multiplication and division use adders as the key components. In order to examine the effectiveness of approximate adders for designing other approximate arithmetic operations, we design an approximate multiplier using approximate adders.
Further, we design an approximate MAC unit using approximate multiplier and adder. We call the resulting approximate MAC unit as “ApproxMAC”. We evaluate the feasibility of ApproxMAC unit in real-life applications through an image processing application.
1.6 Thesis Organization
based). In the end of this chapter, we briefly discuss different directions in which the research work is recently going on in respect to approximate adders.
Chapter 3: AFA-based Approximate Adders
In this chapter, we discuss the proposed AFAs. Further, we present ApproxADD – an N-bit approximate adder designed using the proposed AFAs. We explain our strategies (concept of carry- lifetime and EDC logic) used to improve the ED and ER of ApproxADD. In this way, we introduce two more (improved) versions of ApproxADD – ApproxADDv1 and ApproxADDv2. We provide analytical models to estimate the accuracy, delay, power and area of ApproxADDs. We validate the proposed analytical models through simulation results. We evaluate the effectiveness of the proposed ApproxADDs by comparing them with existing AFA-based approximate adders. Further, in order to inspect the effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression using ApproxADDv2.
Chapter 4: ESA-based Approximate Adders
In this chapter, we discuss the proposed analytical models to estimate the accuracy (ED, ER, MED and MSE), delay, power and area of ESAs. We validate the proposed analytical models by comparing them with simulation results as well as with existing analytical models. Based on the analytical models and simulation results, we discuss some important observations regarding the design metrics of ESAs. Further, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of anN-bit ESA which provide minimal delay, power and/or area for a given accuracy. In the end, we discuss modified ESAs.
Chapter 5: Application of Approximate Adders
In this chapter, we evaluate the effectiveness of approximate adders in cryptography applications, yield enhancement and designing other approximate arithmetic operations. We present an approxi- mate SHA-1 (ApproxSHA-1) and a framework to determine the maximum level of approximation in ApproxSHA-1. Further, we discuss the proposed analytical models to estimate the functional yield and parametric yield of approximate arithmetic circuits. Based on the proposed analytical models, we
1. Introduction
demonstrate the yield enhancement in respect to ApproxADDs. In the end, we present an approximate MAC unit (ApproxMAC) and its feasibility in real-life applications.
Chapter 6: Conclusion and Future Aspects
In this chapter, we conclude the work presented in this thesis. In addition to the contributions and benefits of this thesis, we also discuss some of the very important design challenges and future aspects of approximate adders (AFAs, ESAs, ACAs and VLSAs).
2
Literature Survey
Contents
2.1 Design Philosophy . . . . 22 2.2 Design Approach . . . . 23 2.3 State-of-the-Art AFAs . . . . 24 2.4 State-of-the-Art ESAs . . . . 33 2.5 Research Directions . . . . 37 2.6 Summary . . . . 39
2. Literature Survey
There are two fundamental approaches used for designing the approximate adders: (i) AFA; and (ii) ESA. We briefly discussed these approaches in Chapter 1. Over the past decade, several approx- imate adders have been proposed in the literature based on these approaches [1–4, 12, 14, 56–72].
In this Chapter, we first discuss the design philosophy and design approach of approximate adders.
Further, we present a survey of state-of-the-art AFA-based and ESA-based approximate adders. We also briefly discuss different directions in which the recent research work is going on in respect to approximate adders. In the end, we summarize the Chapter.
The rest of this Chapter is organized as follows. Section 2.1 presents the design philosophy and Section 2.2 presents the design approach of approximate adders. Section 2.3 and Section 2.4 provide the literature survey of AFAs and ESAs, respectively. Section 2.5 discusses the research directions of approximate adders. Finally, Section 2.6 concludes the Chapter.
2.1 Design Philosophy
We know that the critical path in conventional adders depends on the length of carry propagation.
In the worst-case scenario, carry generates at LSBs and propagates to MSBs. In such conditions, the length of carry propagation is close to bit-width. However, in real-life applications, such conditions rarely happen and in most of the cases, the length of carry propagation is much shorter as compared to the bit-width. It has been observed that in most of the cases, the longest length of carry propagation in an N-bit conventional adder is close tolog2N [62, 94, 95] and is less thanlog2N + 12[61] with extremely high probability. In order to evaluate the length of carry propagation, we implementN-bit conventional adders in C/C++ for different values ofN. We then simulate them individually for one billion pseudo-random inputs drawn from a sample space between 0 and 2N −1. Our simulation results forN = 8,16,32,64and128are tabulated in Table 2.1. It can be seen from Table 2.1 that in 99%cases, the length of carry propagation is less thanlog2N +C, whereCis a bit-width dependent constant. Consequently, in anN-bit conventional adder, if carry is computed by consideringlog2N+ C input bits on the right of ith bit position, then the probability of getting correct carry at ith bit position is greater than99%. Further, asCincreases, the probability of getting correct carry increases.
For example, in a 64-bit conventional adder, for C = 1, the probability of getting correct carry is