2. Basics of AlGaN/GaN HEMTs and Numerical Analysis
significant performance degradation. Even the failure rate of GaN-HEMTs is linked with peak temperature in the device. The failure of GaN-HEMTs can be caused by temperature and field dependent phenomena. However, it is generally accepted that temperature dominates on almost all the phenomena responsible for performance degradation. Hence, for ensuring reliable operation and mitigating the chances of time-dependent or device failure, GaN-HEMTs are usually mandated to operate below “safe” levels of power, current and temperature. The maximum permissible channel temperature, TMAX, not only determines the maximum power delivering capability and expected life of the device, but it also plays a crucial role in the design of heat sinks, device packaging, etc. [56]. Therefore, self-heating is extremely important for the prediction of device performance, assessment of lifetime and reliability, system design, etc. Two out of the above mentioned three parameters determining the device “safe” operation region, i.e. output power and current, can be easily measured, but the determination of temperature distribution across the device [57] and identification of hotspots are not easy.
In order to determine lattice temperature equation 2.25 can be utilized. A number of effective solutions to tackle self-heating problem have been proposed in the literature. No- table among these are: (a) altering the substrate material to improve heat dissipation [58];
(b) employing heat sink layers in the device made up of good thermal conductors, such as nanocrystalline diamond [59] etc.; (c) using an exterior heat sink over the entire chip [60] and (d) depositing a quilt-like structure over the entire transistor [61].
2.7.2 Current Collapse
Current collapse denotes the phenomenon where current degrades with an increase in the dynamic resistance and is depicted as a mismatch between output power measured at DC and RF conditions. It is also referred as current compression, current slump or DC/RF dispersion as shown in Fig. 2.9. This leads to the reduction of RF gain of the device, output RF power, dynamic transconductance [62, 63] and device efficiency in the high frequency regime. The existence of traps at the surface, in the buffer or in the barrier layer plays an important role in
2.7 Challenges
Drain Voltage (V)
Drain Current (A/mm)
Collapse VGS_2
VGS_1
VGS_2 > VGS_1
Figure 2.9: Pictorial representation of ID vs VD characteristics for AlGaN/GaN HEMT devices (solid line and dotted line represents before and after the current collapse, respectively)
To better understand the phenomenon of current collapse, the concept of virtual gate mod- eling can be employed [64]. The explanation of device behavior (trapping mechanism) under the influence of gate bias is shown in Fig. 2.10. For an applied negative bias gate voltage (Fig.
2.10(b)), which is below the pinch–off voltage (region A), the peak high electric field induced in the device occurs at the gate edge toward the drain. This leads to the leakage of electrons that fills ionized donor states (on the surface) close to gate electrode, as a result the surface potential becomes negative and channel underneath depletes. The negative surface potential extends the depletion region and behaves as a virtual gate.
In region B, as the gate bias starts becoming positive, the channel under gate electrode must appear (turn–on), but virtual gate effect hinders the quick response (Fig. 2.10(c)). The delay in response to the applied gate bias depends on the detrapping process of the surface traps. Even though gate bias is positive, the drain region is depleted and contains low carrier concentration.This makes drain region to behave as a highly resistive region and majority of the applied potential appear across here, which results in the low drain current.
However, eventually after some period of time (region C), the captured electrons are emitted from the trap and this helps drain current to reach steady state (Fig. 2.10(d)). Therefore, when electric field is sufficiently high, it fills surface traps, which makes the response of the device slow. Thus, a certain time is required for the device to obtain the maximum drain current, which
2. Basics of AlGaN/GaN HEMTs and Numerical Analysis
determines feasibility of high frequency operation. When a device is operated in the pulsed bias condition, influence of trapping and detrapping is quite evident. The trapping phenomenon depends on the applied quiescent bias, while detrapping is observed during turn on pulse. The current collapse phenomenon affects the high power switching applications as well as degrades RF performance of the device. The gradual increase in the resistance of drain access region and knee voltage contributes to the power dissipation even in switched OFF conditions. There are various methods proposed in the literature to mitigate the issue of current collapse, such as surface passivation and the introduction of field plates [2, 65]. While surface passivation helps in the optimal dielectric semiconductor interfacing to prevent filling of surface traps, field plates distribute the electrical field over drain access region, thereby, shifting the peak electric field from the gate edge facing the drain side.
Thermode
S D
AlGaN G
GaN
[0001]
X Y Ionized surface donors
2DEG
(a)
0V 0V 0V
Thermode
S D
AlGaN G
GaN
[0001]
X Y Virtual gate
2DEG Depletion region
Electron leakage
(b)
0V -ve < V_pinch-off +ve
Thermode
S D
AlGaN G
GaN
[0001]
X Y Virtual gate
2DEG Depletion region
(c)
0V +ve +ve
Thermode
S D
AlGaN G
GaN
[0001]
X Y Ionized surface donors
2DEG
(d)
0V +ve +ve A B C
IDS VGS
(e)
V_pinch-off
Figure 2.10: Current collapse phenomenon (with trap behavior) for the bias conditions: (a) Zero bias condition; (b) Negative bias condition (below pinch–off) (Region A); (c) Positive bias (Region B);
(d) when the device is completed turned-on (Region C) and (e) Timing diagram for different regions (bias) of device operation