6.3 Results & Discussion
6.3.3 Self Heating
As it is extensively discussed in the preceding section about the behaviour of devices un- der “SEMI-ON” state, it is equally essential to explore self heating behaviour of the devices as well. Although GaN has higher thermal stability as compared to Si [232], heating effect reduces mobility of electrons in the channel, which subsequently lowers drain current [48, 233].
This hinders prolonged use of GaN-HEMTs under such condition. As we know, degradation mechanisms in AlGaN/GaN HEMTs are thermally initiated and are accelerated [30]. At a higher drain bias, due to high temperature and accumulation of heat, wavefunction of electron
6.3 Results & Discussion
HEMT from the hotspot region increases thermal stress in AlGaN and GaN layers [179]. It is to mention that the degradation mechanism is of diffusive nature because its generation and evolution are directly proportional to the square of time [30]. It has been reported that devices, which are subjected to high temperature for a prolonged duration, exhibit degradation initiated by converse piezoelectric effect and are further accelerated by the high temperature [90].
Field Plate Gate
Lattice Temperature (K)
300 320 340 360 380 400 420
440 Electric Field (V/cm)
0 2e+05 4e+05 6e+05 8e+05 1e+06 1.2e+06
Along the Channel
0.5 1 1.5 2 2.5 3 3.5
Latice Temperature Electric Field FP Edge
FP Edge Gate
TD Model
Figure 6.14: Self heating phenomena in R1 device and lattice temperature along with electric field profile of the device at VGS = 0V and VDS = 20V
Self heating behaviour is observed in a device, when it is operated in the ON state. As we know, AlGaN/GaN HEMT is ON at VGS = 0V, the self heating is observed under bias conditions, VGS = 0V andVDS = 20V as shown in Fig. 6.14. The mathematical models, which need to be plugged into the numerical analysis framework to observe self heating is described in Section 6.2.
Drain Current (A/mm)
0 0.2 0.4 0.6 0.8 1
Drain Voltage (V)
0 10 20 30 40
R1 (TD)
tSiN = 30 nm, tDia = 30 nm (TD) R1 (DD)
tSiN = 30 nm, tDia = 30 nm (DD)
0.88 0.92 0.96
35 36 37 38 39 40
Figure 6.15: Output characteristics of the devices without (R1) and with SiO2 pocket (tSiN =tDia
= 30 nm) depicting the self heating effect, at VGS = 0 V and VDS = 20 V
6. Access Region Stack Engineering for Mitigation of Degradation in AlGaN/GaN HEMTs with Field Plate
The simultaneous solution of lattice temperature with current density equations exhibits a practical lattice temperature distribution. This carrier transport model incorporates device self-heating phenomenon. The ID−VDS characteristics of the devices with the incorporation of thermodynamics model is shown in Fig. 6.15. It is evident that the impact of self heating in the output characteristics is less in the device with SiO2 pocket as compared to R1 device.
This is mainly due to subdued degradation of mobility of the carriers in the former device. As a result, drain current increases while channel temperature deceases in the devices having SiO2 pocket. Hence, this device is expected to have better performance at higher temperature.
Field Plate Field Plate
Figure 6.16: Self heating phenomena; (a) R1 device, and (b) device with SiO2 pocket (tSiN = tDia
= 30 nm) at VGS = 0 V and VDS = 20 V
Moreover, to illustrate the effect of self-heating phenomenon using ID−VDScharacteristics, Fig. 6.15 showcases ID−VDS characteristics with and without thermodynamics model. The absence of thermodynamics model in the equations exhibiting device characteristics transforms them to drift-diffusion model. As we know that this model does not account thermal effects, the evaluation of current densities by thermodynamics and drift-diffusion models are different.
Hence, ID−VDS characteristics of both the above mentioned models differ. Similarly, lattice temperature profiles of R1 device and the device having SiO2 pocket are shown in Fig. 6.16. It is observed that SiO2 pocket in AlGaN/GaN HEMTs aids in reducing hotspots and improves device performance as well as longevity. It is to mention that the lattice temperatures at the field plate edge of R1 device and device with SiO2 pocket (tSiN =tDia= 30 nm) are 437 K and 382 K, respectively.
6.3 Results & Discussion
Lattice Temperature (K)
320 340 360 380 400 420 440
Along the Channel
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7
R1
tSiN = 30 nm, tDia = 30 nm tSiN = 30 nm, tDia = 40 nm tSiN = 30 nm, tDia = 50 nm
(a)
FPEdge
TD Model
Lattice Temperature (K)
350 360 370 380 390 400
Thickness of SiN Layer, tSiN (nm)
10 20 30 40 50
tDia = 30 nm
tDia = 40 nm
tDia = 50 nm
(b) 396
390
382
376 372 379
365 373
369 366
361 362
357 354
353
Figure 6.17: Lattice Temperature comparison of (a) R1 device, and device with SiO2 pocket fortSiN
= 30 nm, (b) combination of tSiN and tDia
Diamond (tDia nm)
Al0.25Ga0.75N Barrier (18 nm)
GaN Buffer (1.7 um) Y=0
SiC Substrate (5 um) X=0
[0001]
X Y S
G
D
LG = 0.25 um LFP = 1 um LGD = 2.7 um LSG = 0.8 um
GaN Cap (2 nm) GaN Channel (30 nm) Si3N4 (tSiN nm)
SiO2
T2 T1
Figure 6.18: Depiction of T1 and T2 for estimation of RTH
It is necessary to extract thermal resistance (RTH) in order to understand the behaviour of heat conduction in a device. The thermal resistance is calculated by considering temperatures at two different points. First point, T1, is the location of a hotspot and the second point, T2 is the region having uniform temperature distribution, refer Fig. ??. Here, we have considered bottom of GaN Buffer or top of the SiC substrate as T2. The temperature drop (∆T = T1−T2) is related to thermal resistance given by Eq. 6.13.
∆T =RT H ×PDissipation, or RT H = T1−T2
PDissipation
(6.13)
6. Access Region Stack Engineering for Mitigation of Degradation in AlGaN/GaN HEMTs with Field Plate
where, PDissipationis the power dissipation in the device. The bias condition for the evaluation of thermal resistance, RT H, are VGS = 0V and VDS = 20V. Employing the self heating profiles of the devices shown in Fig. 6.16, RT H is estimated and is shown in Table 6.8. The lattice temperature profiles of the devices with respect to the thickness of SiN and diamond layers are shown in Fig. 6.17. Moreover, Fourier’s law of heat conduction states that the rate of heat flow is inversely proportional to the thermal resistance [234], which indicates that the heat flow improvises with lower thermal resistance. Further, lower RT H also implies that the proposed device can operate at higher ambient temperature with reduced mechanical deformation due to low lattice vibrations [210]. Thermal resistance of the devices with respect to the thickness of SiN and diamond layer is shown in Fig. 6.19. This indicates that a device with SiO2 pocket offers less thermal resistance and improves its reliability. This can be corroborated with the findings of [210, 235].
Table 6.8: Estimation of Thermal Resistance, RTH for R1 device, and device with SiO2 pocket Device Structure T1(K) T2(K) IDS(A) VDS(V) PDissipation(W) RTH = PT1−T2
Dissipation (K/W)
R1 [6] 437 318 0.95 20 19 6.26
With SiO2
Pocket, tSiN = tDia = 30 nm
382 317 0.98 20 19.6 3.31
Thermal Resistance (K/W)
1.5 2 2.5 3 3.5 4 4.5
Thickness of SiN Layer, tSiN (nm)
10 20 30 40 50
tDia = 30 nm tDia = 40 nm tDia = 50 nm 4.05
2.46 3.73
2.86 2.25
3.31
2.65 2.04
3.00 2.49
1.88 2.79
2.28 1.82 3.17
Figure 6.19: Thermal Resistance, RTH for the device with SiO2 pocket with varyingtSiN andtDia