2.4.7 Challenges and Objectives
The inherent cyclic path in each row and column of a Torus NoC makes the topology deadlock prone. VCs or extra buffers need to used for developing a deadlock free routing algorithm in Torus NoC. Though, Up*/Down* routing approach avoid deadlock without using additional resources [10], routing paths are mostly non minimal or lengthy [94]. In FirstHop routing, a packet is allowed to use the wraparound channel only at its first hop so that cyclic path is discontinued for avoiding deadlock in Torus NoC [1]. Therefore, the leverage of wraparound channels are not utilised for most of the packets. To the best of our knowledge, there is no other approach available for avoiding deadlock in Torus NoC without additional buffer or virtual channels (VC). The objective identified from this back- ground study is to work on a deadlock avoidance approach for Torus NoC without using any additional buffer or VC and at the same time increase utility of wraparound channels.
Detecting confirmed deadlock with an exact deadlock scenario is a challenging task due to the huge state space of NoC [41]. Popular NoC simulator like Booksim [24] and Gem5 [25]
report a warning message for possible deadlock scenarios based on a predefined threshold value. It is very helpful to get the exact deadlock scenario after a deadlock is detected.
This deadlock scenario would be helpful is formulating deadlock avoidance. A formal model of NoC considering detailed NoC components would be helpful to detect confirmed deadlock along with deadlock scenarios. One objective of this thesis is to develop a deadlock detection framework using formal model of NoC considering NoC component in detail.
sources. There is a scope for developing deterministic deadlock free routing algorithms for Torus NoC. In this thesis we will address these problems.
3
Formal Modeling of NoC using FSM and Verification of Starvation using Model Checker
3.1 Introduction
Modeling NoC components in detail level is essential for formal verification to ensure that an NoC works correctly after manufacturing of the real hardware. Modeling NoC close to hardware functionality and scalability of the verification method are the two primary challenges in NoC verification. In most of the existing NoC verification works, detailed modeling of the complete NoC is system is missing [31–34,36,38,39,101]. We have considered NoC functional units in a comprehensive way in this thesis. It is convenient to implement
NoC using Finite State Machine (FSM) in a model checker like NuSMV [22]. Therefore, we have chosen FSM for modeling NoC so that the model can be easily encoded and various properties can be checked using a state-of-the-art model checker.
R1 R2 R3
R4 R5 R6
R7 R8 R9
Processor
Router
(a) 3x3 Mesh NoC
North (N)
South (S)
East (E)
(b) Five ports in a router West (W)
Local (L)
Figure 3.1: A 3x3 Mesh NoC and five bidirectional ports in a router
3.1.1 NoC Router Components
A 3x3 mesh NoC with routers and the connected processors is shown in Fig. 3.1(a).
R1, R2, R3, etc., are the routers shown with square boxes. The brown oval shaped units represent the processors. Each router constitutes of buffers for storing packets, switch for computing the route for a packet and diverting it to desired output port and an arbiter to control the transmission of packets via an output port. We have considered NoC functional units or NoC components like buffer, switch and arbiter for modeling NoC. An NoC works with help of the collaborative efforts between all these units. Buffers are present at the input ports of a router. The five bidirectional ports in a router are shown in Fig. 3.1(b). They are used as temporary storage for a packet before being transmitted in the desired path.
The route computation of a packet is performed by another functional unit called switch.
After the route computation is performed, the packet requests for the expected output port.
There may be multiple packets competing for the same output port at the same time. In
each output port, anarbiter is present that resolves the conflict by picking one packet from the competing packets. The selected packet is transmitted to the next router.
In NoC context, the output port and its connection to the next router are considered as a resource of conflict. If multiple packets from different input ports in a router try to access that output port continuously, there should be fairness such that competing packets from all input ports get a fair chance to be transmitted. This is called starvation-freedom.
Starvation-freedom ensures fairness in resource allocation for the packets from all input ports. In this chapter, we present verification of starvation-freedom using our FSM based NoC model.
3.1.2 Contributions
We have modeled an NoC using FSM, considering buffer, switch and arbiter as individual functional units. Synchronization between these functional units is maintained using ded- icated FSMs. As an application of our model, we target verification of starvation-freedom considering fixed-priority and round-robin arbiters in this work. We encode our FSM based NoC models in NuSMV model checker [22] and give the starvation-freedom specification using Linear Temporal Logic (LTL) [43] for verification. The model checker reports if the given property is satisfied or not. Specifically, the contribution of our work is summarized as follows:
• Detailed modeling of NoC router components like buffer, switch, arbiter using FSMs are presented.
• Demonstrate the designing of fixed-priority and round-robin arbitration policies using FSMs for selecting a packet from more than one competing packets.
• For the correctness of the NoC model, verification of synchronization within a router, progress between NoC components and loss-less transfer of packets are performed.
• As an application of the FSM based model, verification of starvation-freedom for fixed- priority and round-robin arbitration are demonstrated.
• Verification time is reduced significantly by invoking parallel threads for individual routers.
The rest of this chapter is organized as follows. A brief description of FSM and the short form used for describing NoC model is presented in Section 3.2. Formal modeling of NoC using FSM is presented in Section 3.3. Verifying the correctness of the FSM model is described in Section 3.4. Application of the FSM model is described in Section 3.5.
Experimental results are presented in Section 3.6. Finally, we conclude the chapter in Section 3.7.