1.4 Contributions of the Thesis
1.4.4 Deadlock Free Routing Algorithms for Torus NoC using Arc Model . 19
The fourth work of this thesis is the application of Arc model for designing deadlock free routing for Torus NoC. With the help of DDG analysis and CFSM based framework, we have already identified 14 deadlock free Arc pairs with respect to XY-Turns. Therefore, 14 deadlock free routing algorithms are possible using different Arc pairs with XY-Turns. We
have presented one of them in this work. FirstHop [1] and Up*/Down* [10] routing are two other approaches for deadlock avoidance in Torus that do not use additional buffer or VC as like Arc model. We compare Arc based algorithm with FirstHop and Up*/Down*
methods. The wraparound channels are helpful in saving overall hop count in a given traffic. Experimentally it is found that algorithm with two Arcs save more hop counts in comparison to Up*/Down* routing. In FirstHop routing [1], since a packet is allowed to use the wraparound channel only at its first hop, saving in hop count depends upon the percentage of traffic originated from boundary router. There are more percentage of boundary routers in a smaller Torus NoC. The percentage of boundary routers decreases with the increase of NoC grid size. Therefore, saving in hop count also decreases significantly with increase of NoC size in case of FirstHop algorithm. In our Arc based algorithm, saving in hop counts are not affected drastically by the changes in NoC size. The saving in hop counts by algorithms with two Arcs are closer to FirstHop algorithm. We have enhanced our Arc based algorithm by using three Arcs with XY-Turns. The saving in hop count by algorithm with three Arc is better than that of FirstHop algorithm for NoC with grid size 9x9 onward. To improve further, we have used three Arc based algorithm with FirstHop approach by applying it for one wraparound channel. The resultant algorithm further improves the saving in hop counts. We have used DDG to prove deadlock freedom for the proposed Arc based algorithms. No deadlock is detected as well for Arc based algorithms by the CFSM based framework while different input traffic patterns are applied.
1.5 Organization of the Thesis
The thesis is organized as follows:
Chapter 1 Introduction, motivation and contribution of the thesis are presented in this chapter.
Chapter 2 Detailed literature survey on formal modeling and verification of NoC, NoC routing algorithms, existing works on deadlock detection and avoidance approaches are pre- sented in this chapter. We have identified research gaps in those areas and stated our
objectives to bridge them.
Chapter 3Formal modeling of NoC using FSM, verifying correctness of the NoC model and application of the FSM model in verifying starvation-freedom are presented in this chapter.
Chapter 4Detailed modeling of NoC components using CFSM and automated NoC model generation are presented in this chapter. Detection of application specific confirmed dead- lock with deadlock scenario using a CFSM based NoC model is also presented.
Chapter 5 Deadlock avoidance using Arc model for Torus NoC is presented in this chap- ter. DDG is also presented for representing and analysing deadlock with Turn and direction information.
Chapter 6Application of Arc model in designing deadlock free routing algorithm for Torus NoC is presented in this chapter.
Chapter 7 The thesis concludes in this chapter indicating the scope for future direction of our research.
2
Background and Literature Survey
In this chapter we have discussed the existing works related to our research. At first, we discuss about formal verification techniques. For applying formal methods, formal modeling of the system is the prerequisite. An overview of existing works on formal modeling and ver- ification of NoC is then presented in this chapter. Application of the existing formal models in detection of starvation, progress, deadlock along with the limitation of those approaches are also presented. We have discussed the challenges and research gap in formal modeling and verification of NoCs based on the existing works and then stated our objective. Next, we have briefly described about different routing algorithms for NoC. Deadlock freedom is an important aspect of NoC routing algorithms. The state-of-the-art works on deadlock avoidance approaches for NoC routing algorithms are presented. Research gaps for deadlock
avoidance in Torus NoC are also identified. To bridge the research gap, we have identified our objectives in this chapter.
2.1 Formal Verification Techniques
Simulation and testing are widely used for verifying the correct functionality of System-on- Chip (SoC) and NoC. Formal methods have potential to offer early integration of verification in the design phase of an SoC and NoC [43]. The growing complexity and the pressure to reduce development cycle (time-to-market) make the delivery of no-defect system is an enormously challenging activity. Preventing bugs in hardware design has more importance.
Because, hardware is subject to high fabrication cost and fixing them after delivery to customer is very costly and sometimes is not feasible. Whereas, software bugs can be handled by providing users with new updates or patches. Manufacturing of bug free products are essential to the growth and even survival of a company. In the early nineties, due to the floating point division unit bug in Intel’s Pentium II, the company has to replace processors.
This bug cost a loss of approximately 475 million US dollars and damaged Intel’s reputation.
Such errors when occurs in safety-critical control system such as chemical plants, nuclear power plants, automated traffic controller can have catastrophic consequences as well. The Ariane-5 space launch vehicle by European Space Agency (ESA) was crashed in 36 seconds on June 4, 1996. For the software flow in the controller of a radiation therapy machine named Therac-25 causes overdose of radiation. As a result six cancer patients were died during 1985 and 1987. Investigations on these incidence have shown that formal verification procedures would have detect the error in Ariane-5 space launch vehicle, Intel’s Pentium II processor and Therac-25 radiation machine beforehand.