(which will block the execution of system) and hence, to obtain a non-blocking sub-part of M0, we apply supervisor synthesis algorithm [77]. The resulting model M1 contains all feasible scheduling sequences that satisfy the given constraints. It may happen that the state set ofM1 to be empty, which implies that the given task set is non-schedulable under the given set of constraints. Since,M1 contains all feasible scheduling sequences, it allows the leverage of narrowing down further on the subset of the most desired schedules with respect to a chosen set of softer constraints related power, weight, cost etc. Finally, scheduling sequences obtained using our framework are then employed to supervise on-line task execution.
It may be noted that the number of states in the composite models increasesexponen- tially as the number of tasks, processors, execution times increases. So, the proposed scheme may be highly time consuming and unacceptably memory intensive even for moderately large systems, thus severely restricting scalability, especially for industrial applications with many tasks. Over the years, Binary Decision Diagram (BDD) [21] ) based symbolic synthesis mechanisms have proved to be a key technique towards the efficient computation of large finite state machine models including SCTDES based su- pervisors [77]. This observation motivated us to derive a symbolic computation based adaptation of the proposed scheduler synthesis framework. Hence, we have also trans- formed our proposed framework to compute the supervisor symbolically.
1.4 Contributions
As a part of the research work, multiple scheduler design schemes for safety-critical systems have been developed based on SCTDES framework.
1. Scheduling of Real-time Tasks on a Uniprocessor Platform
We have developed models that can be used to synthesize schedulers for aperiodic / sporadic tasks executing (non-preemptively / preemptively) on uniprocessors, and they are listed as follows:
(a) Real-time Scheduling of Non-preemptive Sporadic Tasks
This work proposes an optimal scheduler synthesis framework for non-preemptive
sporadic real-time tasks executing on uniprocessors. Although, in recent years, there has been a few significant works dealing with real-time scheduling using SCTDES, this is possibly the first work which addresses the scheduler synthesis problem for sporadic tasks.
With respect to our proposed framework (ref. Figure 1.1), this work considers the following input parameters: aperiodic as well as sporadic task set, unipro- cessor platform, timing and resource constraints, and directly represents mod- els in TDES form. Here, task execution model captures the execution time, co-execution of tasks and uniprocessor resource constraint. Deadline con- straint associated with a real-time task is captured by a specification model.
(b) Work-conserving Scheduler Synthesis of Preemptive Tasks
This work attempts to synthesize a work-conserving preemptive scheduler for a set of real-time sporadic tasks executing on uniprocessors. Work-conserving approach allows the synthesis of schedules which avoid processor idling in the presence of ready to execute tasks.
2. Fault-tolerant Scheduling of Preemptive tasks on Multiprocessors A methodology for synthesizing an optimal preemptive multiprocessor aperiodic task scheduler using a formal supervisory control framework, is presented. The scheduler can tolerate single/multiple permanent processor faults. With respect to scheduler synthesis schemes developed for uniprocessor systems, the state space of the final supervisor model increases drastically as the number of processors in the system increases. Hence, the synthesis framework has been further em- powered with a novel BDD-based symbolic computation mechanism to control the exponential state-space complexity of the optimal exhaustive enumeration-oriented synthesis methodology [21, 76, 77].
3. Power-aware Real-time Scheduling
This work presents a scheduler synthesis framework which guarantees adherence to a system level peak power constraint while allowing optimal resource utilization
1.4 Contributions
in multi-cores. All steps starting from individual models to construction of the scheduler have been implemented through BDD-based symbolic computation [101].
The synthesis framework has been extended to handle tasks with phased execution behavior [67].
With respect to our framework summarized in Figure 1.1, this work considers the following input parameters: periodic task set, homogeneous multi-core platform, timing, resource and power constraints, and represents models in ATG form. Here, task execution model captures the execution time and deadline of a task. Unipro- cessor resource constraint is captured by specification model. From the resulting set of timing and resource constraint satisfying sequences, we conduct a search technique to filter our the sequences that violate power constraint and we also find execution sequences that dissipate minimal power.
4. Scheduling of Non-preemptive Tasks on Heterogeneous Multi-cores Real-time systems are increasingly being implemented on heterogeneous multi- core platforms in which the same piece of software may require different amounts of time to execute on different processing cores. Computation of optimal schedules for such systems is non-trivial and prohibitively expensive to be conducted on-line.
This work presents a systematic way of designing an optimal off-line scheduler for systems consisting of a set of independent non-preemptive periodic tasks executing on heterogeneous multi-cores. Existing SCTDES based scheduler synthesis mech- anisms do not provide the flexibility to model heterogeneity of the underlying platform. The models developed in this work are able to accurately capture the execution of tasks on a heterogeneous platform. The models can then be employed to synthesize a scheduler to supervise on-line task execution.
5. Static Scheduling of Parallel Real-time Tasks
All our earlier works assume the tasks in a given real-time system to be indepen- dent. However, many real-time applications such as radar tracking, autonomous driving, and video surveillance, are highly parallelizable [44]. One of the most
generic mechanisms for modeling parallel real-time applications is Precedence- constrained Task Graph (PTG)/Directed Acyclic Graph (DAG) [34]. This work deals with the synthesis of an optimal real-time scheduler for PTGs executing on homogeneous multi-cores. We extend our scheme to provide robustness against multiple transient processor faults. Further, we show that the proposed framework can be adapted to derive the best set of schedules with respect to one or multiple performance objectives and demonstrate this idea by devising search strategies to obtain schedules that, (i) minimize makespan and (ii) maximize fault-tolerance.
Conducted experiments reveal the practical efficacy of our scheme.