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Challenges
Scheduling schemes for safety-critical real-time systems must be able to guarantee the timing requirements (i.e., deadlines) associated with different types of tasks coexisting in the system. Scheduling schemes designed for real-time systems must be able to effectively use the processing capacity of.
Objectives
Proposed Framework
Similarly, the composite specification model H can be obtained from individual models that capture the constraints such as timing, resources, etc. To find all sequences in the composite system model T that satisfy the constraints modeled by the composite specification model H, their composite specification model H must be obtained. model is obtained.
Contributions
This work attempts to synthesize a job-saving preemptive scheduler for a set of real-time sporadic tasks running on uniprocessors. This work deals with the synthesis of an optimal real-time scheduler for PTGs running on homogeneous multi-cores.
Organization of the Thesis
This thesis is oriented towards the synthesis of schedulers for safety-critical real-time systems consisting of a set of tasks with strict time constraints executed on a shared computing platform with a limited number of processing elements. In this background chapter, we present a brief introduction to the definitions related to real-time systems and supervisory control.
Real-time Systems
- The Application Layer
- A Real-time Scheduler
- Processing Platform
- A brief survey of scheduling algorithms
Computation Time or Execution Time (Ei) is the time it takes for the processor to execute the task without interruption. Utilization factor U: Given a set of tasks (with an implicit deadline), Γ ={τ1, τ2, .., τn}, U is the fraction of processor time spent executing the task set.
Supervisory Control of Timed Discrete Event Systems
- Activity Transition Graph (ATG)
- Timed Discrete Event Systems (TDES)
- Example
- Behavior of TDES
- Reachability, Co-reachability, Composition
- Supervisory Control
- Supervisor Computation
Then, Algorithm 2 (CO-REACHABLE) is called to compute the set of co-reachable states in M, denoted by Q0. Next, Algorithm 1 calls Algorithm 3 (NON-CO-REACHABLE), which first computes the initial set of non-co-reachable states in M through Q\Q0, denoted by SQi.
In Algorithm 1, Q00 is added to the set of unsafe conditions Qiu and is iteratively extended until the fixpoint is reached.
NON-CO-REACHABLE Input: M , The set of co-reachable states Q 0
- Tools
- Summary
- Related Works
- Non-preemptive Scheduler Synthesis Framework
- Aperiodic Tasks with Known Arrival Times
- Task execution model
In the above command, EX AT12 TIMED represents the name of the resulting composite model. The tuple (23,30) represents the total number of states and transitions present in the composite model. Based on the above approach, we construct the TDES models for all the naperiodic tasks in the system.
- Deadline Specification for an Aperiodic Task
- Supervisor Synthesis
- Handling Arbitrary Aperiodic Task Arrivals
- Handling Dynamically Arriving Sporadic Tasks
- Application Example
- Preemptive Scheduler Synthesis Framework
- Task execution model
- Composite Task Execution Model
- Removal of Non-work-conserving Sequences
The TDES Hi model shown in Figure 3.4 captures the specification of the aperiodic task deadline τi. Next, we perform product assembly to obtain a composite hand specification model H=H1||H2||..||Hn. i) The marked behavior Lm(H) represented by the composite deadline specification model includes all execution sequences of meeting the deadline for all tasks in I. ii). This model includes a set of states in addition to the states already present in Hi (shown in Figure 3.7(b)) to capture the minimum interarrival time limit.
Timing Specification Model
After one tick event, SHi reaches state 2, in which the self-loop is similar to that in state 1. Therefore, {pi, ei} is allowed only up to the ticks Di−Ei from the arrival of τi, which is covered by the self-loop transitions present in states 1 to 5. In state 13, the own loop Σ\Σi allows the possibility of the next instance of the task τi arriving at will.
Composite Timing Specification Model
To illustrate this fact, let us try to find the deadline-missing sequence seq7 =a1p1a2p2e1te1tc1te2tc2t ∈Lm(T0) in the composite model SH shown in Figure 3.18. More specifically, after processing sub-stringa1p1a2p2e1te1tc1tofseq7, the next event in seq7 ise2. Now consider the deadline meeting, sporadic sequence seq9 =a1p1a2p2e2tc2te1te1ta2p2 c1te2tc2tt∈Lm(T0).
Scheduler Synthesis
Although Lm(M) is a deadline, missing-deadline sequences in T0 and resource-constraint-violating sequences in SH lead to deadlock states in M, i.e. M blocks. To ensure that all accepted tasks meet their individual deadlines, the scheduler must be designed to achieve Lm(M), ie. the scheduler must be able to prevent reaching any unreachable state M that may lead to deadlock states. Specifically, M must be controlled by disabling certain controlled events (ri, pi,ei, and ci) that are present in the corresponding states so that none of the deadlock states in M is reached.
M 0 CONSTRUCTION
Case Study: Instrument Control System
Summary
In the next section, we discuss the synthesis of a fault-tolerant scheduler for a set of real-time tasks running on a homogeneous multiprocessor platform. In the previous chapter, we assumed that the underlying hardware processing platform is flawless. To this end, we extend the models developed in the previous chapter from a single-processor to a multi-processor platform and empower them with the ability to tolerate a single persistent processor failure.
Related Works
Proposed Scheme
- Assumptions on System Model
- A TDES model of task execution under single fault
- Problem formulation for scheduler design
- A TDES model of deadline specification
If the scheduler activates the rejection event ri (and deactivates pi), then Ti returns to the initial state from State #4 and remains in that state until either the occurrence of the next release (or arrival) event (ai) or either of the processors' liability. For example, if Ti is at State #1, then an error from the processor V1 will take Ti to State. As mentioned earlier, this model represents all possible deadline sequences of the task set I.
M 0 CONSTRUCTION Input: M , n (number of tasks)
Complexity Analysis & Symbolic Computation using BDDusing BDD
- Symbolic representation of TDESs using BDDs
- Example for Symbolic Computation of Supervisor
Computation of states inχM7→0 (represented by BDD χQ00) convergent to deadlock states inχblock through uncontrollable event using PreImage-uc (χblok, χM7→0. Computation of safe states inM0 (represented by BDDχQs) using a forward reach- .Bounded (χQ00, χq0M0, χM7→0 )3 to remove the safe states in Similarly, the set of states which can reach the remaining states in χQ00 in one uncontrollable transition will be obtained.
Handling multiple faults
The No Error substructure is not shown in Figure 4.11, as it is the same as Figure 4.1. The Single Fault structure shown in Figure 4.11 now contains outgoing transitions on fault events to allow another fault. Let us assume that Ti is initially at State #5 of the No Fault Structure (shown in Figure 4.1) for both cases.
Comparative Study
Even for the cases of errors in 2 and 3 processors, the proposed scheme still maintains an acceptance rate of 100%. However, as the number of errors increases, the decrease in acceptance ratio also becomes inevitable for our scheme due to system overload (i.e., ρ(t) = 9.25>8). However, it can be noted that in all cases the decrease in acceptance rate in [86] is larger than in the proposed scheme.
Summary
For example, if you compare the drops in acceptance rates for a single error while increasing the number of incoming tasks from 10 to 24 (24 to 30), it can be noted that the proposed scheme has a 0% (10%) drop. In summary, the study shows that as the system load increases (due to an increase in the number of tasks, an increase in the number of processor errors, etc.), the difference in acceptance ratio of the proposed scheme with that of [86] increases. The results obtained above may vary depending on the task set in question, the arrival pattern of the tasks, the number of processors, the time of occurrence and the number of errors, etc.
Related Works
Proposed Framework
- Task Execution Model
- Resource-constraint Model
- Finding Resource-constraint Satisfying Sequences
- Finding Power-Constraint Satisfying Sequences
- Peak Power Minimization
- Complexity Analysis
- Symbolic Computation using BDD
- PEAK POWER-AWARE SYMBOLIC SYNTHESIS Input: BDD χ M 1 (= χ M 1
- Modeling Window Based Power Consumption
Finally, we denote the resulting model consisting of a set of safely attainable states in M1 as M2. The state space complexity of the resource constraint model RCi (in Figure 5.5) is O(n) because it contains different states associated with the initial state that represent the execution of each task in the processor core Vi. A modified version of the task execution model Ti,act, which adequately captures the windowed execution of task τi, is shown in Figure 5.12.
Window Based Resource-constraint Model
It should be noted that the execution of any task (say τx) is not preemptive and therefore all its windows are executed continuously in sequence without any interruption on the same processor until completion. Therefore, RCk captures only the start of the execution of the 1st window (sx,1,k) and the completion of the execution of the last window (cx,Lx) associated with τx.
Window Based Scheduler Synthesis
This means that the chip power dissipated in a given state qx now depends on the power constraints Bi,j corresponding to the currently active execution windows Wi,j associated with each running task in state qx. It should be noted that during this updating process, the phase-insensitive version of the PAS algorithm considered only the worst-case power dissipation Bi, instead of Bi,j. The MINIMIZE PEAK-POWER DISSIPATION algorithm (Algorithm 8) remains almost the same for window-based scheduler synthesis with one small change.
Complexity Analysis
Specifically, the initial lower bound on maximum power is now given by the maximum power cap over all windows of all tasks, i.e., Bmin = max. To handle the exponential state space complexity associated with the synthesis process, we can use the symbolic synthesis scheme presented in Section 5.3. These changes ensure that the execution of a window-based task is correctly captured when calculating the peak power distribution in the system.
Experimental Results
As is clear, the size of the models increases as the number of tasks and/or the number of processors grows. Being optimal in nature, our scheme is more efficient in minimizing the peak power compared to the other two state-of-the-art approaches. For each system configuration, we measured the acceptance ratio, i.e. the ratio between the number of task sets considered schedulable and the number of task sets presented to.
Summary
In the next chapter, we consider the scheduling synthesis for a set of real-time tasks executed on a heterogeneous multi-core platform. In the previous chapters, we have assumed that the processing cores in a multi-core platform are identical (ie homogeneous). In this chapter, we consider the optimal scheduling of a set of non-preemptive real-time tasks executed on a heterogeneous multicore.
Related Works
As mentioned earlier in this thesis, we apply a supervisory control approach to planner synthesis. Although there have been a number of important works dealing with real-time scheduling using supervisory control in recent years, this may be the first work to address the problem of scheduler synthesis for non-preemptive periodic tasks.
Proposed Scheduler Synthesis Scheme
- Task Execution Model (ATG)
- Task Execution Model (TDES)
- Composite Task Execution Model
- Resource-constraint Model
- Supervisor Synthesis
- Example
Then P Ti,act returns to activity READY upon the arrival of the next instance of τi (ai) and τi continues its execution in a similar manner. It can be noted (from Figure 6.2) that the arrival of the first instance of τi (i.e. fai) occurs at Athi tick from the start of the system. In this case, P Gi contains exactly Pi−Ei,1 ticks between the completion eventci,1 and the arrival of the next instance ofτi.
Summary
In the previous chapters of this dissertation, we discussed the real-time scheduling of independent tasks on a multiprocessor / multicore platform. One of the most generic mechanisms for modeling parallel real-time applications is priority constrained task graphs (PTGs)/directed acyclic graphs (DAGs). In this chapter, we present a scheduler synthesis framework for a parallel real-time application represented by PTG , running on a multi-core platform.
Related Works
It can be noted that SCTDES-based existing scheduling synthesis works can handle a variety of real-time and fault-tolerant scheduling schemes. 29] Periodic Non-preemptive Uniprocessor Does not consider task priorities [53] Periodic Both Uniprocessor Considers task priorities [87] Periodic &. Sporadic non-preemptive Uniprocessor It correctly captures the time constraints between arrivals. [105] Periodic Preemptive Uniprocessor It supports multiple tasks.
Scheduler Synthesis for PTGs
- Scheduler Synthesis Scheme
- Composite Task Execution Model
State #2 to State #4: States similar to State #1 are replicated |∗c|times (from State #1 to State #3) to model the completion of all the immediate antecedents. States similar to state #1 are replicated |∗c| times (from state #1 to state #4) to model the completion of all the predecessor nodes of τn+1. The model T represents the overall execution of PTG G0, starting from its source node, through all the intermediate nodes, and culminating in the completion of its sink node.
Timing Specification Model
After the number of Ecri ticks has elapsed from the arrival of the current instance, H reaches state #5. These tick events force the expiration of at least P ticks from the arrival of the current instance, after which H reaches state #12. Therefore, the completion event c6 is only allowed after 4 ticks from the occurrence of the arrival event a.
Scheduler Synthesis
![Figure 3.9: A simple motor network adopted from [29].](https://thumb-ap.123doks.com/thumbv2/azpdfnet/10540589.0/82.892.119.738.169.733/figure-3-9-simple-motor-network-adopted-29.webp)
