Non-preemptive Scheduler Synthesis Framework

ALGORITHM 3: NON-CO-REACHABLE Input: M , The set of co-reachable states Q 0

3.2 Non-preemptive Scheduler Synthesis Framework

of sporadic tasks.

Table 3.1 provides the summary of qualitative comparison between the state-of-the- art SCTDES based uniprocessor scheduling schemes. Although the scheduler synthesis approaches presented in [85, 87] attempt to handle sporadic tasks, they fail to correctly model minimum inter-arrival time constraint. In this chapter, we present scheduler synthesis framework which has the ability to correctly model sporadic tasks.

Table 3.1: Comparison between SCTDES based uniprocessor scheduling schemes

Method Tasks Preemptive /

Non-preemptive Remarks

[29] Periodic Non-preemptive It considers non-preemptive periodic tasks.

[53] Periodic Both It considers both preemptive & non-preemptive tasks.

[105] Periodic Preemptive It considers tasks with multiple periods.

[106] Periodic Conditionally

preemptive It considers conditionally preemptive tasks.

[85] Sporadic Preemptive It does not capture minimum inter-arrival time constraint of sporadic tasks.

[87] Periodic,

Sporadic Preemptive It does not correctly model periodic as well as sporadic tasks.

Section 3.2 Aperiodic,

Sporadic Non-preemptive It correctly captures minimum inter-arrival time constraint of sporadic tasks.

Section 3.3 Sporadic Preemptive It correctly captures minimum inter-arrival time constraint of sporadic tasks.

3.2 Non-preemptive Scheduler Synthesis Framework

In this section, we present the synthesis framework for the design of an optimal non- preemptive scheduler for a set of: (i) aperiodic tasks with known arrival times, (ii) dynamically arriving aperiodic tasks, and (iii) dynamically arriving sporadic tasks.

3.2.1 Aperiodic Tasks with Known Arrival Times

System Model: We consider a real-time system consisting of a set I (= {τ₁, τ₂, ..., τ_n}) of n (≥ 1) non-preemptive, aperiodic tasks to be scheduled on a uniprocessor [31, 47, 54, 54]. Formally, the task τ_i to be scheduled is represented by a 3-tuplehA_i, E_i, D_ii, where A_i is the arrival time, E_i is the execution time and D_i is the relative deadline of τ_i.

Assumptions: (1) Tasks are independent with no precedence constraints [30]. (2) Execution time for each task is constant and equal to its worst-case execution time WCET [73]. (3) E_i ≤ D_i for all tasks in I. (4) All tasks are reported to the scheduler

which then controls their execution on the uniprocessor according to the pre-computed off-line scheduling policy.

3.2.2 Task execution model

0

∑\

(∑iU{t})

a_i s_i

4 5 t 6 c_i

# t = Ei

1 t

∑\

(∑iU{t})

2

∑\

(∑iU{t})

t t ₃

∑\∑i

# t = Ai

∑uc\ {ai}

∑uc\ {ai}

∑uc\ {ai}

7

∑\∑i

Figure 3.1: Task execution modelT_i for task τ_i hA_i, E_i, D_ii.

The TDES model T_i for executing a non-preemptive, aperiodic taskτ_i hA_i, E_i, D_iiis (shown in Figure 3.1) defined as,

T_i = (Q_i, Σ, δ_i, q₀, Q_m),

where, Q_i = {0,1, ...,7}¹, q₀ = 0, Q_m = {7}, Σ = ∪i∈{1,2,...,n}Σ_i ∪ {t}, where Σ_i = {ai, si, ci}. The events are described in Table 3.2 and they are categorized as follows: (i) Σuc=∪i∈{1,2,...,n}{ai}, (ii) Σc = Σ\(Σuc∪{t}), (iii) Σf or = Σc. Since the arrival events of tasks are induced by the environment, they are modeled asuncontrollable events. Apart from Σ_uc and tick event (t), remaining events in the system are modeled as controllable events. These controllable events are also modeled asforcible events which can preempt the tick event (t). All events in Σ are considered to be observable.

Table 3.2: Description of events (for non-preemptive execution)

Event Description ai Arrival of a taskτi

si Start of execution ofτi

ci Completion of execution ofτi

State 0 is the initial state ofT_i and represents the state in which taskτ_i resides prior to the start of the system. Events in the self-loop Σ\(Σ_i∪ {t}) may be characterized

1The states are numbered sequentially starting from 0, for illustration purpose. However, the total number of states inT_i for a given task τ_i will vary depending on its execution time.

3.2 Non-preemptive Scheduler Synthesis Framework

as follows: Since τ_i has not yet arrived, the events that are associated with τ_i (Σ_i) are excluded from Σ. To elaborate, the self-loop contains the events such as arrival, start of execution, and completion with respect to any other task (τ_j ∈I, j 6=i) in the system.

Thus, Σ\(Σ_i ∪ {t}) does not impose any restriction on the execution of other tasks.

State 0 is replicated Ai times in order to measure the occurrence of Ai ticks subsequent to system start.

After the occurrence of ai at Aith

tick, Ti reaches State 3 from State 2. Here, the scheduler takes a decision whether to immediately allocate the task τi for execution on a processor or make it wait on the ready queue. The latter is indicated by the self- loop transition Σ\Σ_i at State 3. If the scheduler decides to start the execution of τ_i, then it will enable the event s_i to assign τ_i for execution on the processor. According to Figure 3.1, if event s_i occurs at State 3, then T_i reaches State 4. At State 4, the self-loop transition Σ_uc\ {a_i} ensures that only arrivals (barring that of τ_i) but not the execution of tasks other than τ_i are allowed. This is because τ_i has already started its non-preemptive execution on the processor. After the elapse of E_i ticks from State 4, Ti reaches State 6. Finally, the event ci which is used to mark the completion of τi’s execution, takes Ti to the marked state State 7. Now, Ti continues to stay at State 7 without imposing any constraint on other tasks currently executing on the processor.

It may be noted that τi consumes exactly Ei ticks from the start of its execution at State 4. However, τ_i may miss its deadline based on the amount of time spent in the ready-queue at State 3. Suppose τ_i stays at State 3 for x ticks before s_i, then (i) τ_i is deadline-meeting if (x+E_i) ≤ D_i, (ii) τ_i is deadline-missing if (x+E_i) > D_i. Hence, L_m(T_i) contains both deadline-meeting as well as deadline-missing execution sequences for task τ_i. Now, let us formally introduce the notion of a deadline-meeting sequence as it is relevant for our discussion.

Definition: Deadline-meeting sequence (with respect to non-preemptive execution):

A sequence s = s₁a_is₂c_is₃ ∈ L_m(T_i), where s₁, s₃ ∈ Σ^∗, s₂ ∈ (Σ\ {c_i})^∗ is deadline- meeting, if tickcount(s₂)≤ D_i. Otherwise,s is a deadline-missing sequence.

Example: Now, we illustrate the generalized task execution model discussed above

using an example. Let us consider an example (adopted from [23]) uniprocessor system consisting of two tasks τ₁h0,4,7i, τ₂h1,2,4i. The task execution models T₁ for τ₁, T₂ for τ₂ are shown in Figures 3.2(a) and 3.2(b), respectively. It can be observed that the arrival ofτ₁ (i.e.,a₁) takes place at system start. Onceτ₁ has started execution (i.e., s₁), it consumes exactly 4 ticks to complete its execution (i.e., c1). During τ1’s execution, only the arrival ofτ₂ is allowed until its completion which is modeled by the self-loopsa₂ at states 2 through 6. Similarly, it can be observed from Figure 3.2(b) that the arrival of τ₂ takes place at the first tick subsequent to system start and it takes 2 ticks to complete

its execution after the start of its execution.

a1 s1 2 3 t 6 c1

# t = 4

0 t

∑\(∑1U{t})

1

∑\∑1

7

∑\∑₁ a2 a2

4

a2 5

a2

t t

a2

a2 s2 3 4 t 5 c2

# t = 2

1 t

∑\(∑2U{t})

2

∑\∑₂

6

∑\∑₂

a1 a1 a1

0

∑\(∑2U{t}) t (a):

(b):

# t = 1

00 a₁ 10 11 12

t a2

s₂ 13

s₁ 20

t 31a_{2 32}

21a2 22

s1

s1

t

t 42 t ₅₂ t ₆₂ (c):

t 14 t ₁₅c2 ₁₆ s1 26 t 36 t 46 t 56 t 66

72 73 74 75

76

c₁ s2 t t

c₂ c₁ t

t

t

t

Figure 3.2: TDES Models: (a) T₁ for τ₁, (b) T₂ for τ₂, (c) T =T₁||T₂

Based on the above approach, we construct the TDES models for all the naperiodic tasks in the system. Given thesenindividual TDES task modelsT₁,T₂, ...,T_n, a product composition T = T₁||T₂||...||T_n on the models gives us the composite model for all the tasks executing concurrently.

Remark 3.2.1. (i) The marked behavior Lm(T) represented by the composite task execution model includes both deadline-meeting as well as deadline-missing execution sequences for all tasks in I. (ii) It may be observed that T_i allows only one task for execution on the processor at any instant (which satisfies resource constraint). Specifi- cally, whenτ_i has started its execution (i.e.,s_i) atState 3, only the arrival of other tasks

3.2 Non-preemptive Scheduler Synthesis Framework

00

a

1 10 11 12

t a

2

s

2 13

s

1 20

t

31

a

2 ₃₂ 21

a

2 22

s

1

s

1

t

t

42

t

₅₂

t

₆₂

T:

t

14

t

₁₅

c

2 ₁₆

s

1 26

t

36

t

46

t

56

t

66

72 73 74 75

76

c

1

s

2

t t

c

2

c

1

t

t

t

t

t t

0 1 2 3 4 5 6 7 8

τ

₁

τ

2

t t

0 1 2 3 4 5 6 7 8

τ

₁

τ

₂ Deadline miss

seq

₁

:

seq

1

= a

1

s

1

t a

2

t t t c

1

s

2

t t c

2

(Deadline-missing)