1.9 Organization of Thesis
2.1.2 Emerging Non-Volatile Memory Technology
Chapter 2. Background 25
Chapter 2. Background 26
MgO Refrence Layer
Free Layer
(a)
(1) (2)
MgO Refrence Layer
Free Layer
IWL IWL
BL BL
MTJ MTJ
SL SL
Vwrite1 Vwrite0/Vread
(c) (d)
(b) Bit-line (BL)
NMOS
Source-line (SL) Word
-line (W L) Bipolar Write Pulse
/ Generator
Ref. Sense A
mp.
MTJ
Free Layer Refrence Layer
Figure 2.4: (a). Conceptual view of STT-RAM cell (b) Schematic STT view with (1) Write ‘1’ operation (2) Write ‘0’ and Read operation (c) Parallel low resistance, representing ‘0’ state (d) Anti-parallel high resistance, representing
‘1’ state
Read Operation: To access the state of the STT cell, the access transistor of the cell is enabled and the small voltage difference is established between the lines (source and bit line) (figure 2.4 (b) (2)). This effect causes the current to be generated across the memory cell, which is compared with the reference current through the sense amplifier.
Write Operation: To write bit ‘0’, a large positive voltage difference is estab- lished between the source and bit line (figure 2.4 (b) (2)). To write bit ‘1’, a large negative voltage is established between the lines (figure 2.4 (b) (1)).
The other important characteristics of STT-RAM are summarized below:
1. STT-RAM tries to attain better scalability by using different write mecha- nism based on spin polarization [40].
2. The STT-RAM cells have more density compared to SRAM, but have lesser density compared to DRAM [41].
3. Compared to PCRAM and ReRAM, the endurance of STT-RAM is excellent.
However, when employed in the cache the endurance is still consider to be less [20].
Chapter 2. Background 27 4. The write operation of STT-RAM are costlier with respect to SRAM and
DRAM [41].
Other than the design characteristics, the STT-RAM chip is commercially manu- factured and available in the market. For instances, 4Gbit STT-RAM based per- pendicular MTJ at 90nm technology node is fabricated by Toshiba and SkHynix incorporation [42]. Qualcomm and TDK-Headway built the 1Mbit STT at 40nm technology node [43]. Recently, Intel and Samsung fabricated 7.2M and 8M bit STT at 22 and 28 nm technology nodes [44, 45] respectively.
In this thesis, the terms STT-RAM or STT and PCRAM or PRAM are used interchangeably.
2.1.2.2 Phase Change Random Access Memory (PCRAM)
Currently the most mature emerging NVM technology that is under research is the Phase Change Random Access Memory (PCRAM) [46]. Figure 2.5 shows the representational view of PCRAM cell. The PCRAM cell contains phase change or chalcogenide material and an access transistor. The chalcogenide material is generally made up of GST (Ge2Sb2T e5, or Germanium, Antimony and Tellurium) and shows two different phases: Amorphous and Crystalline by the application of heat. The high electrical resistivity characterizes amorphous phase and represents the RESET state of the cell. On the other side, the crystalline phase is charac- terized by low electrical resistivity and represents the SET state of the cell. The read and write operation of the PCRAM cell are described below:
Read Operation: To access the state of cell, a small voltage is applied across GST. This effect causes the current to be generated as there is a wide resistance gap exist between the amorphous and crystalline phase. The state of the cell is identified by sensing the pass through current with the help of access transistor and the word-line controlling.
Write Operation: To SET the PCRAM cell, a long duration moderate power
Chapter 2. Background 28
BL
WL GST
SL
Top Electrode
Substrate GST
N+ Heater
Bottom Electrode
Figure 2.5: Representational view of PCRAM cell
pulse is applied that heats the GST above the crystalline temperature and makes the chalcogenide material crystalline. On the other side, to RESET the PCRAM cell, a high power pulse is applied that heats the GST above the melting temper- ature and makes the chalcogenide material amorphous.
The other important characteristics of PCRAM are as follows:
1. Due to the significant difference in resistance between the different phases of GST, the PCRAM cell can be used to store the multi-bit information [47].
2. PCRAM is a scalable technology because as the feature density increases, it needs less current for the operations [48].
3. The SET and RESET latency of the PCRAM is larger than the STT-RAM and DRAM [20].
4. The endurance of PCRAM is bound to the limited number of writes. The current write endurance value varies in the range of 104writes to 109writes [49].
The commercial industries focus on PCRAM as a replacement of flash memory technology or to be used as the main memory. Different types of PCRAM chips at different technology nodes are manufactured and fabricated. For example, at 90nm node, Samsung electronics built the 512 Mb PCRAM chip with 266 Mb/s band- width [50]. Later, Samsung fabricated the 8Gb PCRAM chip at 20 nm technology with 40 Mb/s program bandwidth [51].
Chapter 2. Background 29
Pt
Pt +
-
+
-
V TiO2-x
TiO2 Top electrode
Bottom electrode Low Oxygen Vacancy
Concentration High Oxygen Vacancy
Concentration
Figure 2.6: Representational view of ReRAM cell
2.1.2.3 Resistive Random Access Memory (ReRAM)
ReRAM [52] is based on the memristor technology where the resistance change de- pends upon the polarity, magnitude, and the duration of the applied voltage. Fig- ure 2.6 shows the representational view of the ReRAM cell. The memristor-based ReRAM cell consists of two platinum electrodes with titanium dioxide (T iO2) metal/oxide interference switches having different oxygen vacancy concentrations.
Generally, the metal/oxide interference shows rectifying behavior with low doping and ohmic behavior with high doping [53]. In particular, the lower switch of per- fect titanium dioxide (T iO2) is electrically insulating and the upper switch, which has high having oxygen vacancy concentration (T iO2−x) is conductive. The read and write operation of the ReRAM cell are described below:
Read Operation: To access the state of ReRAM cell, a small voltage is applied across the bit lines. This effect causes the current to be generated that can be sensed to detect the particular state of the cell.
Write Operation: To change the state of the cell, a large voltage is applied across the bit lines. To change the state of the cell to OFF, a negative bias voltage is used which increases the thickness ofT iO2, which in turn generates the insulating and high resistance ion path. The opposite case is seen in case of positive bias voltage for the ON state.
The other important properties of ReRAM cell are as follows:
1. The ReRAM memory technology is less mature than the PCRAM and STT- RAM memory technologies [54].
Chapter 2. Background 30 2. In the terms of scalability, ReRAM is more efficient compared to STT-RAM and PCRAM. The cell size of 10nm has been achieved and in future, the cell density of 4-5nm is predicted [55, 56].
3. The write endurance of ReRAM is limited to 105 to 1011 writes which is lesser than the STT-RAM and some of the prototypes of PCRAM [56, 20].
The ReRAM technology is still not as mature as other emerging NVMs and is currently under research. Recently, only Fujitsu and Panasonic are jointly working on the second generation ReRAM device [57].