For each of the component present in the CMP, the total power consumption can be divided into three categories [12, 13, 14]: (1) Static Power, (2) Dynamic Power, and (3) Short Circuit Power.
1.4.1 Static Power
The static power is defined as the power drawn by the on-chip circuitry, even when the circuitry is not performing any task. Static power resembles the leakage power of the circuit, which is based on two important leakage units: (1) Gate Leakage, and (2) Sub-threshold leakage [14, 15, 16, 17]. Between these two units, the sub- threshold leakage has a direct relation with the chip temperature and the supply voltage. As the chip temperature becomes higher, the covalent bond of the atoms in the semiconductor material is broken that releases the electrons which flows in the reverse bias and generates the current, called the sub-threshold leakage current.
The power drawn due to the sub-threshold current is called sub-threshold leakage power. Whereas, the gate leakage power is due to the down-scaling of device size and the reduction in the thickness of gate oxide material. The direct relation of running chip temperature and supply voltage on the sub-threshold leakage is presented in the following equation [18, 15]:
Pstat =K1VDDT2e(λVDD+β)/T))+K2e(γVDD+δ) (1.2)
In the eq. (1.2),Pstatrepresents the static power consumption due to sub-threshold leakage by a CMOS circuit. T denotes the current temperature and VDD implies the supply voltage. K1,K2,λ,β,γ, andδare the empirical constant that represent the different circuits parameters.
Chapter 1. Introduction 7
1.4.2 Dynamic Power
The dynamic power is defined as the power consumed due to on-chip circuity while performing the task. It is due to the switching activity of the transistor while charging/discharging the output capacitances. The dynamic power is represented by the help of the following equation [14, 15]:
PDyn=α.C.V2.f (1.3)
In the eq. (1.3), PDyn denotes dynamic power of cores. The parameters α, C, V and f represent the activity factor, capacitance, supply voltage and frequency of the core, respectively.
For the on-chip caches, the dynamic power is consumed during the cache access.
The cache is accessed either for the write operation or for the read operation.
In the traditional cache (fabricated from the SRAM/DRAM), the read and write access power consumption are same [13, 19]. Whereas, with the advancement of the semiconductor technologies, researchers have also considers the emerging Non-Volatile Memory (NVM) technologies for the caches. In these NVM caches, the access power for the read and write operation is asymmetric [20, 21, 22].
The detailed modeling of the power consumption for different types of memory technologies used for the fabrication of the cache is discussed in Chapter 2.
Whereas, for the NoC, the major chunk of dynamic power is consumed by two basic units: (1) Routers, and (2) Connecting Links. Among these two units, the routers are the most complex part of the system that uses multiple routing algorithms for sending the data optimally across the chip. The data is passed through the connecting link, which is nothing but a set of metallic wires. During the routing operation, the dynamic power consumed by the router is due to the following three units [23]:
1. Router Clock: The essential part of the router that maintains the synchro- nization.
Chapter 1. Introduction 8 2. FIFO Buffers: The buffer maintains the sequence/order of incoming/out-
going data blocks in the router.
3. Arbiters and Allocators: Make sure that the data block reaches to the proper destinations.
1.4.3 Short-Circuit Power
The short circuit power is defined as the power consumed due to non-zero fall/rise time of the CMOS circuitry. In particular, it is the power consumed during the short-time span when both NMOS and PMOS are active simultaneously. The short circuit power consumption is very negligible and most of the time ignored during the calculation of power consumption of CMPs [14, 15, 16].
This dissertation considers only the static and dynamic power/energy for the calculation of power/energy consumption.
For the modern CMPs, among the different on-chip components, the processing cores are usually accounted for high dynamic power consumption. Whereas, the on-chip caches fabricated from the SRAM/DRAM are considered for their high leakage energy. Also, in the modern CMPs, it has been noticed that the as the size SRAM/DRAM cache become larger, the number of transistor increases and occupies large wafer real estate area. This leads to large leakage power consump- tion which becomes the significant contributor in the total power consumption of the chip. Table 1.1 presents the percentage power contribution by the on-chip SRAM caches with respect to the total power consumed by the chip [12, 24].
These large numbers in the table motivate the computer architects to reduce the power consumption by the on-chip caches. This thesis focuses upon reducing the high leakage power consumption of the on-chip SRAM caches by employing the emerging near-zero leakage power NVM caches.
Chapter 1. Introduction 9
Microprocessor Power Consumed by on-chip Caches with respect to total power
ARM 920T 44%
Strong ARM SA-110 27%
21164 DEC Alpha 25-30%
Niagra 12%
Niagra2 21%
Alpha 21364 13%
Xeon (Tulsa) 13%
Table 1.1: Power consumed by on-chip caches