Enhancement of SBST Techniques for Detection of Processor Faults

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Complexity of Modern Digital Circuits

If an error is discovered somewhere in the circuit after the manufacturing process, the entire chip is discarded. Thus, the remote test method using high-frequency test capability of remote ATE has become more expensive and less feasible due to the high test data volume and longer test application time.

Digital Testing Principles

Even after the chip is commercialized, the testing process must continue to ensure that the chip performs properly during normal operation for safety-critical and industrial applications. For a high-frequency operating chip, a high-frequency test capability of ATE is required, and the size of the physical memory of ATE must be large enough to store a large number of test patterns and responses.

Processor Testing and its Challenges

Structural testing methods could use an electronic design automation (EDA) tool to generate ATPG test sequences using structured DFT techniques such as the chain scan method. Later, the concept of self-testing was introduced, which minimizes yield loss by actually testing at speed while keeping the overall cost of testing the processor lower.

External Testing to Self-testing: A Paradigm ShiftShift

SBST of Processors

With the help of information from phase A, the processor components are classified in phase B as functional, control and hidden components. For self-test synthesis in phase C, we collect ISA information and component information from phase A and component test priority information from phase B.

Principal Scheme of SBST Automation

Test Code Preparation in MicroGP Methods

A test solution consists of a sequence of macros and is represented by a DAG, as shown in the example in the figure. A DAG node has pointers to a macro element in the instruction library and a set of parameters as shown in the figure.

Test Quality Evaluation

Gate-level Fault Models

The EDA tools [47] for combinational fault models are mature enough to develop smaller test sets with shorter test application time and shorter fault simulation time. Since the EDA tools for sequential fault models cannot develop efficient test sets, the fault simulation time and test generation time are high for the test sets that detect the sequential faults.

Behavioral Fault Models

External Fault Simulation

Intuitively, the error coverage and error listing of an SBST test program is completely associated with the observability of the processor modules. Later, these answers are compared to the golden answers of the good processor model to assess the error coverage.

Figure 1.7: Test Program Evaluation Overview

Motivation and Objectives

Moreover, the test synthesis would be further delayed if the evolutionary module searched extensively for the hard-to-detect errors. Thus, our goal is to speed up the test synthesis procedure, along with the detection of hard-to-detect errors, by reusing the existing test programs with identical features.

Contributions

In the first preprocessing stage, we remove the independent instructions using a data dependency graph of the test program. Thus, the test code compiled for production testing is replaced by many small and efficient test codes with sufficient fault coverage.

Organization of the Thesis

Furthermore, we elaborate on the recent progress in the three most important phases of the SBST procedure, which are SBST code synthesis, optimization, and application (phases C, D, and E), as shown in Figs. The section 2.2.1 and section 2.2.2 of this chapter describe the background for the improvements in the functionalities of SBST code synthesis, section 2.2.3 describes the background of SBST code optimization, and section 2.2.4 describes the background of SBST code application.

Chronology of Processor Testing Methods

This test procedure should be performed at the actual hardware speed of the processor, which is in GHz. In this approach, a sequence of test vectors is selected from all possible test inputs so that these test vectors can detect most processor faults.

Advanced SBST Techniques

SBST Code Synthesis
Faster SBST Code Synthesis
SBST Code Optimization
SBST Code Application

In this approach, fault coverage is improved using feedback from the test evaluation framework. The test pattern generation (TPG) schemes for floating point units are selected according to the target requirements [64].

Summary

But smaller test codes may have smaller error coverage, which may cause some of the intermittent errors to go undetected. So we improve test quality by uncovering the processor's hard-to-test faults using an effective test evaluation method.

Preliminaries and Working Principle

In general, defects in functional components directly related to instructions in the ISA are easily detectable from most instruction sequences. It is relatively challenging to identify defects in the control unit and other non-functional components belonging to the processor control path.

Evolutionary Approach for Test Program Syn- thesisthesis

Testability of Processor Components

The controllability matrix element Cont(i, j) is 1 only if a random value assigned to one of the settable fields in template instance tj is propagated to component inputIi when template instance tj is applied to processor. The above testability definitions are used to derive the selection probability of the instructions as shown in steps 5-8 of Algorithm 2 to be included in the assembly code test program, corresponding to each processor component, during the evolutionary process of test program synthesis.

Figure 3.11: A General Instruction Template

Self Adaptation of Evolutionary Strategies

In general, mutation power is of great value in the initial stages of the search process. So self-adaptive approaches build an improved population that takes advantage of the population traits of previous generations.

Experimental Study for MIPS Processor

Testability and Coverage Evaluation

3.15, we have shown the improvement in the coverage of the controller component errors using the proposed greedy based method compared to the traditional method [2] shown in Fig. This indicates that the convergence rate of the proposed greedy method is less when compared with the traditional µGP technique up to 100 generations.

Figure 3.12: Fault Coverage of Modules Using Traditional µGP [2] on MIPS Processor

A Study on the Effectiveness of Behavioral Fault Models

Let's look at the stuck-at-0 error on the output network of the OR gate as shown in the figure. Thus, the stuck error at 0 OR gate is sensitized as shown in the figure.

Figure 3.17: A Block Diagram of 32-bit ALU of MIPS Processor

Experimental Study for Leon3 Processor

Although the implementation of a Leon3 processor at the gate level is significantly larger and more complex than MIPS, the number of behavioral errors differs slightly. Since the instruction sets of the MIPS processor and the Leon3 processor are equivalent, the number of behavioral errors associated with the ELSE IF blocks is also almost equal.

Figure 3.23: Integer Pipeline Unit of Leon3 Processor [3]

Comparison and Discussions

If the number of arithmetic or logic instructions is large in the ISA of a processor, the number of ELSE IF blocks will be high and eventually the number of behavioral errors related to ELSE IF blocks will also be high. This concept of an almost equal number of behavioral errors in Leon3 and MIPS processors leads to the scalability of the scheme.

Summary

Since the number of behavioral errors does not change significantly with the processor size, the test program generation time is almost equivalent for both processors, which explains the scalability of our scheme.

Overall Approach of RSBST Program Synthesis

The simulation response repository stores the observation values, error coverage, and error list of parent chromosomes. The contents of the observable loci, which are the simulation responses obtained using high-level logic simulation, are contrasted with the observation values of the parent chromosomes to check the extent of reusability of the test program.

Observability-based Reusability of Test Programs

Repository of Simulation Responses

Rij: The content of the registry locations after the execution of the Pij test software solution. Let Fij be the error coverage achieved by the solution of the test program Pij, and let F Cij be the set of errors covered by Pij.

High-level Simulation

Also, in the state before executing the test program, each observable location is initialized to zero. Similarly, procedures of each opcode in the ISA are activated for the logical execution of each instruction.

Observability Comparator

The observability comparator analyzes the contents of the observable locations of a test program and its parent test programs. Also, the memory update corresponding to the test program 1 store instruction is h(r4 + e f set), (r2)i and the memory update corresponding to the test program 2 store instruction is h(r4 + i f set), ( r3)i.

Design of RSBST Scheme

9 Update the simulation repository of Pij with the fault list F Cij and coverage Fij achieved using fault simulation. 10 The fitness function of Pij is |F Nij|, which is the cardinality of the set of its newly covered errors, where F Nij = F Cij - F CCi;.

Experimental Results

Observability Analysis of Test Programs

This module stores the content of observed targets to identify redundant test programs that can be evaluated internally. Now the simulation repository is loaded with the contents of the observed locations (OBSi−1parent1(j)) Pi−1parent1(j) and (OBSi−1parent2(j)) Pi−1parent2(j), which are the parent test programs of Pij.

Case Studies for MIPS Processor and Leon3 Processor

Finally, the µGP approach [2] could detect 92.9% of the faults, and the greedy-based GA comes up with a fault coverage of 95.8%. The coverage and test synthesis time of the five main modules of the MIPS processor.

Figure 4.5: Average Fault Coverage for MIPS Processor and for Leon3 Processor over 400 Generations using 1) µGP [2] with Behavioral Fault Model 2) Greedy-based GA proposed in the last chapter 3) Proposed RSBST

Chromosome Reusability of RSBST

Summary

Faster and deeper test synthesis can be developed using fragmented reuse of test programs. Even if the observability of the 2 test programs is different, identical and data-independent code fragments (chunks) can be extracted from these test programs and reused.

Basics of SBST Compaction

In the first step, the test program is preprocessed using a dependency graph-based independent instruction removal technique. After eliminating independent instructions, we employ a faster, top-to-bottom instruction recovery technique using logic simulation of the test programs in the second stage of test compression.

Redundant Instruction Group Removal Using Data Dependency GraphsData Dependency Graphs

5.2 shows the data dependencies between instructions in a test program developed using automated test synthesis. Initially, the dependencies between instructions of the input test program P are identified to construct a dependency graph G.

Figure 5.1: Data Dependency Graph with Single Connected Component

Enhanced Instruction Restoration Method

Top to Bottom Compaction Policy

After eliminating this redundant instruction, each of its dependent errors is added to the set of dependent errors of the instruction in the lower blocks it detects. Thus, it would be difficult for the lower blocks of instructions to replace a preceding critical instruction that detects many dependent errors.

Restoration Using High-level Logic Simulation

Now, the instruction blocks above the current reset block are replaced with the contents of the initial state. Finally, this initial state replaces the 3 main blocks of the original test program to give the reduced test program.

Figure 5.3: Example of Reducing Test Program Using Logic Simulation

Experimental Results

CRS is the ratio between sizes of the optimized test code and the original test code, and. However, the logical simulation of preceding blocks reduces the cost of the proposed technique faster than that of the existing technique [4].

Figure 5.5: Amount of Compaction for Different Test Programs

Summary

In order to achieve a high quality of self-testing, i.e. high error coverage, self-test codes detect even these occasional errors. If the self-test period is extended, the error detection delay would also increase, and as a result, some current intermittent errors may go undetected.

Figure 6.1: Avg. Execution Time for Different Groups of Fragments on 100 MHz MIPS Processor Model

Preliminaries

Utilization Factor of Real-time Applications
Least Upper Bound
Reliability Analysis
Recovery Scenarios
Worst Case Response Time

Also, the response time in the worst case should not exceed the respective deadline of each task. So, to insert a self-test task into the set of mission tasks, the scheduling must be validated, i.e., the usage and response time conditions must be met for all tasks.

SBST Programs for Intermittent Fault Detec- tiontion

Fragmented SBST for Testing Intermittent Faults

Synthesis of Smaller Latency Self-test Programs with Ad- equate Coverageequate Coverage
Calculation of Test Periods for FTPs
Scheduling of FTPs
Reliability Enhancement Analysis of FTPs
Overall Synthesis of Self-test Fragments

When the self-test subtask S3 identifies an error in the third segment (H3) of the mission task, each input from the system is restored from the previous checkpoint (Cr). The execution window for a self-test subtask corresponds to the subtask period.

Figure 6.3: Time Diagram of Traditional Testing over Period T i

Experimental Results

A Case Study of Reliable Synthesis of FTPs

As the number of FTPs increases in a test period, the size of the execution window decreases. Furthermore, the size of the execution window increases as the coverage of the FTP increases, and vice versa.

Figure 6.6: Replacement of a Test Program of Group G 95 by 4 Smaller Test Programs (FTPs) of Group G 85 for testing the Branch Functionality of a MIPS Processor

Summary

This is confirmed by over 80% reuse of intermediate test programs (chromosomes in the genetic algorithm sense) for both the MIPS and Leon3 processors. In our fourth paper, a set of shorter SBST code fragments with improved reliability were discovered to replace large SBST codes in online processor testing.

Future Works

On the automatic generation of software-based self-test programs for functional testing and diagnosis of VLIW processors. In Proceedings of the conference on Design, automation and testing in Europe: Proceedings, pages 65–70.