The work presented in this thesis leaves several open directions and there is ample scope for future research in the domain of SBST for processors. In this section, we present
7.2 Future Works
four such future perspectives.
• Advanced fault discovery using greedy SBST synthesis: The evolution- ary and greedy concepts of automated SBST synthesis can be extended towards potentially developing a meaningful and profound fault discovering technique for more complex multicore NoCs and SoCs. The computational components of com- plex SoCs can be functionally tested using SBST programs. In Leon3 processor, the floating point components and the coprocessor could also be tested for the completeness of the test process.
• Fragment-wise reusability and fault equivalence techniques: A faster and profound test synthesis could be developed using the fragment-wise reusability of test programs. Even if the observability of two test programs are different, the identical, and data-independent code fragments (chunks) could be extracted from these test programs and reused. Also, the fault equivalence techniques could be used for reducing the volume of simulations and the test generation time. Two faults are equivalent if the output function of a processor module is the same for both of them. So, we classify the equivalent faults into the same group. Also, if a test program could detect one of these faults, it can detect all its equivalent faults.
So, all faults in a group of equivalent faults could be tested using a single fault simulation, which will accelerate the test synthesis.
• Instruction reordering technique could be integrated for further opti- mization: Our work on removal-restoration techniques could be extended by in- tegrating instruction reordering techniques for further optimization of the test pro- gram. We could heuristically search for the optimal ordering of instruction groups with minimum execution time while maintaining the fault coverage. However, this search process must be conducted keeping a threshold on the computational cost.
• Test code optimization by removing common instruction in test sets:
The module-by-module test programs could have instructions that cover common faults. The instructions of a test program for a module may also cover some of the faults of other modules. So, we can extend our test program compaction work by identifying and removing instructions which cover faults that are already covered
by test programs of other modules. To realize this, test programs with the largest excess fault coverage are to be considered first and redundant instructions are to be removed from other test programs. Also, a comparison study for the monolithic test programs and module-by-module test programs, in terms of execution time and size, can be conducted to determine the most efficient online testing approach.
• Scheduling of FTP execution to enhance intermittent fault coverage:
FTP execution time is significantly smaller (<10%) when compared with the mis- sion critical task execution. So, it may generate less heat as compared to mission critical applications but it can detect intermittent faults and raise a flag for fault tolerance. However, differnet execution sequences of FTPs executed in a test pe- riod lead to different power consumption and heat generation, i.e., the execution ordering of FTPs have direct impact on power consumption and temperature of the processor. So, each FTP must be assigned a priority and based on this pri- ority, they must be scheduled during test period interleaving mission application.
Therefore, a study of FTP execution scheduling can be conducted to maximize the intermittent fault coverage.
• SBST techniques for memory consistency testing and validation: Memory consistency models significantly impact the ease of programming a multi-processor system, as well as the set of hardware and compiler optimizations. Commer- cial architectures support a variety of memory models, such as Sequential Con- sistency(SC), Total Store Order(TSO) and Release Consistency(RC). As several complex elements are involved in the memory hierarchy design, memory model testing is a major challenge for memory architects today. There are several ap- proaches for checking the correctness of shared-memory multiprocessor implemen- tations focusing on the memory subsystem. SBST approaches for multiprocessors are able to test the designs with programs whose results can be reasoned about a priori or are precomputable. So, a study on the memory consistency testing can be conducted using various SBST approaches.
• SBST techniques for post-silicon validation and manufacturing testing:
After the processor chip design passes from the pre-silicon verification stage, few chip prototypes are fabricated and these prototypes are used as test objects in the
7.2 Future Works
post-silicon validation stage. Post-silicon validation is in the orders of magnitude faster than simulation-based pre-silicon verification tests. SBST programs may be utilized to enhance the controllability and observability of functional verification tests to develop an effective the post-silicon validation. Production/manufacturing testing screens manufactured chips for physical faults or defects before the chip is released into the market. This testing procedure must be conducted in the actual speed of the processor hardware which is in GHz. As SBST ensures at-speed test- ing of circuits, it is an emerging solution for production test/manufacturing test.
Currently, SBST is used for the at-speed testing of processors in BIST and on- line/concurrent testing methods. So, effective SBST soultions for both production test/manufacturing test and post-silicon validation can also be developed.
• SBST techniques to test unencrypted firmware or software of a com- plex SoC design: Firmware is low-level software which can directly access the physical memory space of its interacting hardware devices. This hardware-specific nature distinguishes it from higher-level software such as the operating system (OS) or application code which is device independent. This higher-level software communicates with the hardware via firmware. The firmware address space is ker- nel accessible but not user accessible and the software address space is assigned separately for each user. Correct functionality of firmware is critical and its mal- function while accessing critical physical memory can crash the OS or even the entire system. For example, bugs in device drivers were considered to be the cause of 85% of the failures of the Windows XP Operating System. This component of the system is increasing in scale and importance, and thus firmware validation is a critical part of system validation. SBST techniques can be developed to validate the firmware and software by testing their concurrency with the interacting SoC hardware modules.
• SBST techniques to test encrypted firmware of a complex SoC design:
The encrypted firmware of complex SoC designs can be validated by developing SBST programs for the encryption hardware for the firmware. When SoC com- ponets are accessed, all memory addresses that are issued by software are virtual.
These memory addresses can be passed to the Memory Management Unit (MMU),
which can check the TLBs for a recently used cached translation. If the MMU does not find a recently cached translation, the table walk unit reads the appropriate ta- ble entry from memory. As MMU ensures authorized access to firmware or software in memory, the integrity of the circuit could be compromised if any faults/defect occur in MMU hardware. To validate encrypted firmware, both encryption hard- ware and MMU hardware can be tested using dedicated SBST programs.
• SBST techniques for validation of trust zones: Trust Zones are embedded security technology that starts at the hardware level by creating two environments that can run simultaneously on a single core: a secure world and a not-as-secure world (non-secure world). ARM TrustZone Trust Execution Environment (TEE) is an implementation of the TEE standard, which offers a execution space of high- level application security. To validate these trust zones, SBST programs can be developed separately based on the level of testability of secure and non-secure environments.
Publications
• Vasudevan Madampu Suryasarman, Santosh Biswas and Aryabartta Sahu, Automation of Test Program Synthesis for Processor Post-silicon Vali- dation, Journal of Electronic Testing, vol.34, no.1, pp.83-103, Feb 2018.
• Vasudevan Madampu Suryasarman, Santosh Biswas and Aryabartta Sahu, RSBST: An Accelerated Automated Software-based Self-test Synthesis for Processor Testing, Journal of Electronic Testing. vol. 35, 695714 (2019).
• Vasudevan M S, Santosh Biswas and Aryabartta Sahu, RSBST: A Rapid Software-based Self-test Methodology for Processor Testing, The 32nd International Conference on VLSI Design 2019.
• Vasudevan Madampu Suryasarman, Santosh Biswas and Aryabartta Sahu,
”Fragmented SBST Technique for Online Intermittent Fault Detection in Processors”. (Provisionally accepted with major revisions in IET Computers
& Digital Techniques)
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