Self-testing could be hardware-based self-testing [29, 30] or software-based self-testing (SBST) [16,22,31,32]. In hardware-based self-testing, also termed asbuilt-in self-testing (BIST), a dedicated hardware module is attached to the processor for testing. This module generates the test patterns and applies them to the module under test (MUT).
Eventually, the responses are collected and delivered to another circuit, which does the response analysis. Deterministic testing or pseudorandom testing could be used for the test generation in BIST approach. However, the on-chip test generation is easier with the help of pseudorandom testing as it produces the test patterns using smaller additional
1.4 External Testing to Self-testing: A Paradigm Shift
Figure 1.2: SBST Procedure
hardware circuits.
Apart from the at-speed testing feature, the transfer of the processor testing approach from external ATE-based approach to an internal BIST mechanism provided significant advantages. One of them is the reduction of test cost earned by the use of self-test methodologies for processor testing. Self-testing reduces yield loss with the help of actual at-speed testing while the overall test cost of the processor is lesser. Also, the use of self- testing drives down the design cycle and therefore, a better time-to-market is achieved.
The Intellectual Property (IP) protection is also improved when compared with that of the scan-based external testing techniques. An apparent drawback of hardware-based self-testing approach is the hardware overhead spent for the additional testing circuit.
Also, during the hardware-based self-testing, power consumption is more than that of the normal operational mode of the chip. To solve this, SBST methodologies [16, 22, 31, 32]
were introduced.
SBST methodologies have cultivated software-based test codes that were applied on the processors as test routines. These test codes are sequences of instructions with se- lected operands that could validate the processor functionality. The SBST approaches are non-intrusive because the chip design or hardware does not necessitate any modifi- cation for testing. These light-weight test codes are uploaded into the memory locations and the responses are downloaded and compared for the fault identification. Further- more, SBST does not require any extra hardware which leads to a reduced test cost and zero chip area penalty [33]. For these reasons, SBST is exceedingly used for embedded processor testing.
The advantages of SBST [28] are:
• At-speed testing: The test program application is performed at the speed of the actual frequency of the processor. Therefore, all physical faults can be detected and the test quality is improved.
• Non-intrusive: SBST does not add any extra hardware or DFT modification over- head to the existing circuitry. It executes normally like all other programs and consumes the same average power during the testing phase.
1.4.1 SBST of Processors
SBST procedure for a processor is as illustrated in Fig. 1.2. The self-test program, which is a sequence of assembly code instructions, is generated using a test pattern synthesis technique [28] and is downloaded into the instruction memory of the chip for testing.
The self-test data and its corresponding responses are stored in the data memory. The test program is executed to generate a test response, which is compacted and stored in the data memory. The response collection and response compaction of SBST require negligible hardware intrusion. Now, the response is analyzed to produce a pass or fail indication, based on which we proceed for further actions on the system. In SBST, the self-test programs are downloaded to the tester memory from a low-cost, low-speed ATE and the test responses uploaded back to the ATE for the response analysis [34].
Recently, several advanced manual SBST approaches [33, 35–37] have been intro- duced for SBST code generation. To automate SBST synthesis, test engineers exploited hierarchical structural testing methods like formal verification [25, 38, 39] which discov- ers input sequences that violate user specifications for the fault detection of each pro- cessor module. Also, functional feedback-based methods like evolutionary approaches are prevalently used in the domain of SBST automation. As structural methods are computationally prohibitive for SBST automation, genetic algorithm-based evolution- ary strategies for SBST automation are used.
1.4.1.1 Phases of SBST Procedure
The overall SBST procedure, as shown in Fig. 1.3, includes the following five phases: A) Information extraction, B)Processor component classification and test prioritization, C)
1.4 External Testing to Self-testing: A Paradigm Shift
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Figure 1.3: Phases of SBST Procedure
Test program synthesis, D) Test program optimization, and E)Test program application.
In phase A, the ISA information and Register Transfer Level (RTL) information of the processor are used to identify the components of the processor and the operations of the components, etc. With the help of the information from phase A, the processor components are classified in phase B as functional, control, and hidden components.
Functional components could be either computational functional modules, such as Arithmetic Logic Unit (ALU), adder, multiplier, etc. or storage functional modules, such as accumulator, register file, etc. Major control components, such as control unit, generate the control signals for the functional components of the processor, thereby con- trolling the data flow and instruction flow. The hidden components, such as pipelining, increase the throughput of instruction execution but are functionally invisible.
These components are prioritized based on accessibility and testability to enhance the test development phase (Phase C). The computational functional components have higher testability than any other components because their operations are directly as- sociated with instruction execution, i.e., they are functionally more visible. So, these components are assigned a higher priority for test development. In phase C, self-test codes are synthesized for each component as a module under test (MUT), based on
the priority. The self-test synthesis is initially conducted for high-priority components because adequate fault coverage has to be achieved as quickly as possible.
For the self-test synthesis in phase C, we gather the ISA information and component information from phase A and the test priority information of components from phase B. However, it is apparent that the test software is an additional process that competes with user processes for system resources, such as central processing unit (CPU) cycles and memory. Therefore, on-line test program execution is considered to be an overhead to overall system performance regarding memory area, power consumption and execu- tion cycles. Also, large size and longer execution time of SBST programs for complex processors make manufacturing test difficult. So, in phase D, the self-test codes (syn- thesized in phase C) are subjected to an optimization procedure in terms of memory footprint, execution time, power consumption, test size, test execution time, etc. In the last phase (phase E), we apply the optimized self-test codes from phase D during the processor manufacturing stage and/or operational stage. The optimized test code with the highest fault coverage is used to test every instance of the same processor chip.